# US 10,120,683 B2 · Supporting even instruction tag (‘ITAG’) requirements in a multi-slice processor using null internal operations (IOPs)

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- Number: US 10,120,683 B2
- Document ID: US10120683B2
- Status: Granted
- Kind: B2
- Application number: 15/139,430
- Filed: 2016-04-27
- Published: 2017-11-02
- Granted: 2018-11-06
- Earliest claimed: 2016-04-27
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Steven R. Carlough; Kurt A. Feiste; Paul M. Kennedy; Phillip G. Williams
- Web page: https://patentgrep.com/patent/US10120683B2

## CPC

- G06F 13/4068: {Electrical coupling}
- G06F 9/30076: {to perform miscellaneous control operations, e.g. NOP}
- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution}
- G06F 9/3853: {of compound instructions}
- G06F 9/3856: {Reordering of instructions, e.g. using queues or age tags}
- G06F 9/3891: {organised in groups of units sharing resources, e.g. clusters}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Supporting even instruction tag (‘ITAG’) requirements in a multi-slice processor with null internal operations (IOPs) includes: receiving an IOP with an even ITAG requirement; determining that the IOP is to be assigned an odd ITAG; and inserting a null IOP into an instruction lane ahead of the IOP, wherein the null IOP is assigned the odd ITAG, and the IOP is assigned an even ITAG.

## Claims

### Claim 1

A method for supporting even instruction tag (‘ITAG’) requirements with null internal operations (IOPs), the method comprising:
receiving an IOP with an even ITAG requirement, wherein the even ITAG requirement is a requirement that the IOP is assigned an even ITAG;
determining that the IOP is to be assigned an odd ITAG; and
inserting a null IOP into an instruction lane ahead of the IOP, wherein the null IOP is assigned the odd ITAG, and the IOP is assigned an even ITAG.

### Claim 2 (depends on 1)

The method of claim 1 wherein determining that the IOP is to be assigned an odd ITAG comprises:
determining, during a previous cycle, that the ITAG assigning unit will assign the IOP an odd ITAG based on a sequential assignment of ITAGs.

### Claim 3 (depends on 1)

The method of claim 1 wherein the IOP is grouped with a companion IOP, and the IOP is received before the companion IOP, and wherein the companion IOP is assigned a subsequent odd ITAG.

### Claim 4 (depends on 3)

The method of claim 3 further comprising:
sending the IOP to a first execution slice; and
sending the companion IOP to a second execution slice.

### Claim 5 (depends on 4)

The method of claim 4 wherein the first execution slice calculates a subsequent odd ITAG assigned to the companion IOP based on the even ITAG assigned to the IOP.

### Claim 6 (depends on 3)

The method of claim 3 wherein the IOP and the companion IOP are each part of a single instruction.

### Claim 7 (depends on 1)

The method of claim 1 further comprising:
sending the null IOP to a completion unit.

### Claim 8

A multi-slice computer processor for supporting even instruction tag (‘ITAG’) requirements with null internal operations (IOPs), the multi-slice computer processor comprising null IOP insertion logic configured to carry out the steps of:
receiving an IOP with an even ITAG requirement, wherein the even ITAG requirement is a requirement that the IOP is assigned an even ITAG;
determining that the IOP is to be assigned an odd ITAG; and
inserting a null IOP into an instruction lane ahead of the IOP, wherein the null IOP is assigned the odd ITAG, and the IOP is assigned an even ITAG.

### Claim 9 (depends on 8)

The multi-slice computer processor of claim 8 wherein determining that the IOP is to be assigned an odd ITAG comprises:
determining, during a previous cycle, that the ITAG assigning unit will assign the IOP an odd ITAG based on a sequential assignment of ITAGs.

### Claim 10 (depends on 8)

The multi-slice computer processor of claim 8 wherein the IOP is grouped with a companion IOP, and the IOP is received before the companion IOP, and wherein the companion IOP is assigned a subsequent odd ITAG.

### Claim 11 (depends on 10)

The multi-slice computer processor of claim 10 further configured for:
sending the IOP to a first execution slice; and
sending the companion IOP to a second execution slice.

### Claim 12 (depends on 11)

The multi-slice computer processor of claim 11 wherein the first execution slice calculates a subsequent odd ITAG assigned to the companion IOP based on the even ITAG assigned to the IOP.

### Claim 13 (depends on 10)

The multi-slice computer processor of claim 10 wherein the IOP and the companion IOP are each part of a single instruction.

### Claim 14 (depends on 8)

The multi-slice computer processor of claim 8 further configured for:
sending the null IOP to a completion unit.

### Claim 15

A computing system including a multi-slice computer processor configured for supporting even instruction tag (‘ITAG’) requirements with null internal operations (IOPs), the multi-slice computer processor comprising null IOP insertion logic configured to carry out the steps of:
receiving an IOP with an even ITAG requirement, wherein the even ITAG requirement is a requirement that the IOP is assigned an even ITAG;
determining that the IOP is to be assigned an odd ITAG; and
inserting a null IOP into an instruction lane ahead of the IOP, wherein the null IOP is assigned the odd ITAG, and the IOP is assigned an even ITAG.

### Claim 16 (depends on 15)

The computing system of claim 15 wherein determining that the IOP is to be assigned an odd ITAG comprises:
determining, during a previous cycle, that the ITAG assigning unit will assign the IOP an odd ITAG based on a sequential assignment of ITAGs.

### Claim 17 (depends on 15)

The computing system of claim 15 wherein the IOP is grouped with a companion IOP, and the IOP is received before the companion IOP, and wherein the companion IOP is assigned a subsequent odd ITAG.

### Claim 18 (depends on 17)

The computing system of claim 17, wherein the multi-slice computer processor further configured to carry out:
sending the IOP to a first execution slice; and
sending the companion IOP to a second execution slice.

### Claim 19 (depends on 18)

The computing system of claim 18 wherein the first execution slice calculates a subsequent odd ITAG assigned to the companion IOP based on the even ITAG assigned to the IOP.

### Claim 20 (depends on 15)

The computing system of claim 15, wherein the multi-slice computer processor further configured to carry out:
sending the null TOP to a completion unit.