# US 10,120,682 B2 · Virtualization in a bi-endian-mode processor architecture > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,120,682 B2 - Document ID: US10120682B2 - Status: Granted - Kind: B2 - Application number: 14/193,610 - Filed: 2014-02-28 - Published: 2015-09-03 - Granted: 2018-11-06 - Earliest claimed: 2014-02-28 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Michael K. Gschwind; Brett Olsson - Web page: https://patentgrep.com/patent/US10120682B2 ## CPC - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/30032: {Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE} - G06F 9/30038: {using a mask} - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/30189: {according to execution mode, e.g. mode flag} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Embodiments of systems disclosed herein relate to processor architecture. One such system implements a method that includes the processor obtaining an instruction. The instruction specifies an operation, and also specifies one of the registers as a source register and one of the registers as a destination register. The method also includes the processor obtaining an endian mode and determining that the instruction is an element-ordering-sensitive instruction. Based on the determination that the instruction is an element-ordering-sensitive instruction, the processor executes the instruction by performing the operation on the elements of the source register in accordance with the endian mode and writing a result of the operation to the destination register. ## Claims ### Claim 1 A computer system for processing vectors, the system comprising: a memory; and a bi-endian mode vector processor including a plurality of registers, each of the registers including a plurality of elements; the computer system configured to perform a method comprising: obtaining, by the processor, an instruction specifying an operation, the instruction further specifying one of the registers as a source register and one of the registers as a destination register; determining, by the processor, whether the instruction is an element-ordering-sensitive instruction; based on determining that the instruction is an element-ordering-sensitive instruction: obtaining, by the processor, an endian mode; and executing the instruction by the processor by performing the operation on the elements of the source register in accordance with the obtained endian mode and writing a result of the operation to the destination register; and based on determining that the instruction is not an element-ordering-sensitive instruction, executing the instruction by the processor by performing the operation on the elements of the source register in accordance with a first endian mode and writing a result of the operation to the destination register. ### Claim 2 (depends on 1) The computer system of claim 1, wherein the source register and the destination register each correspond to a respective vector register. ### Claim 3 (depends on 1) The computer system of claim 1, the computer system further configured for: based on determining that the instruction is an element-ordering-sensitive instruction: determining that the obtained endian mode corresponds to the first endian mode; and based on the determination that the obtained endian mode corresponds to the first endian mode, performing the operation on all elements of the source register sequentially from a leftmost one of the elements of the source register to a rightmost one of the elements of the source register. ### Claim 4 (depends on 1) The computer system of claim 1, the computer system further configured for: based on determining that the instruction is an element-ordering-sensitive instruction determining that the obtained endian mode corresponds to a second endian mode; and based on the determination that the obtained endian mode corresponds to the second endian mode, performing the operation on all of the elements of the source register sequentially from a rightmost one of the elements of the source register to a leftmost one of the elements of the source register. ### Claim 5 (depends on 1) The computer system of claim 1, the computer system further configured for: based on determining that the instruction is an element-ordering-sensitive instruction: modifying a reference in the instruction to one of the elements of the source register in accordance with the obtained endian mode; and performing the operation specified in the instruction with the modified element reference without an additional reference to the obtained endian mode. ### Claim 6 (depends on 1) The computer system of claim 1, the method further comprising: based on determining that the instruction is an element-ordering-sensitive instruction: providing, based on the obtained endian mode corresponding to the first endian mode, an unmodified form of an operand corresponding to at least one of the elements of the source register; modifying, based on the obtained endian mode corresponding to a second endian mode, a first element of the source register, according to the second endian mode, into a second element, according to the first endian mode; and providing the modified source register as an operand. ### Claim 7 (depends on 6) The computer system of claim 6, wherein the modifying inverts at least one of the significant bits of the first element. ### Claim 8 (depends on 1) The computer system of claim 1, the method further comprising: based on determining that the instruction is an element-ordering-sensitive instruction: providing, based on the obtained endian mode corresponding to the first endian mode, a first input operand to a first operand port of the processor and providing a second input operand to a second operand port of the processor; and providing, based on the obtained endian mode corresponding to the second endian mode, a first input operand to the second operand port of the processor and providing a second input operand to the first operand port of the processor. ### Claim 9 (depends on 1) The computer system of claim 1, the method further comprising: based on determining that the instruction is an element-ordering-sensitive instruction: providing, based on the obtained endian mode corresponding to the first endian mode, at least one input operand to circuitry within the processor without modification; reversing, based on the obtained endian mode corresponding to the second endian mode, all elements of the at least one input operand; and providing the reversed at least one input operand to the circuitry within the processor. ### Claim 10 (depends on 1) The computer system of claim 1, the method further comprising: based on determining that the instruction is an element-ordering-sensitive instruction: providing, based on the obtained endian mode corresponding to the first endian mode, at least one output of circuitry within the processor as a result operand of an instruction without modification; modifying, based on the obtained endian mode corresponding to the second endian mode, the output of the circuitry within the processor; and providing the modified output as the result operand of the instruction. ### Claim 11 (depends on 10) The computer system of claim 10, wherein the modifying includes a reversing of all elements of the output.