# US 10,120,680 B2 · Systems, apparatuses, and methods for arithmetic recurrence > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,120,680 B2 - Document ID: US10120680B2 - Status: Granted - Kind: B2 - Application number: 15/396,184 - Filed: 2016-12-30 - Published: 2018-07-05 - Granted: 2018-11-06 - Earliest claimed: 2016-12-30 - Assignees: Intel Corporation - Applicants: Rama Kishan V. Malladi; Elmoustapha Ould-Ahmed-Vall - Inventors: Rama Kishan V. Malladi; Elmoustapha Ould-Ahmed-Vall - Web page: https://patentgrep.com/patent/US10120680B2 ## CPC - G06F 9/3001: {Arithmetic instructions} - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/30038: {using a mask} - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/30101: {Special purpose registers} - G06F 9/3016: {Decoding the operand specifier, e.g. specifier format} - G06F 9/3017: {Runtime instruction translation, e.g. macros} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Embodiments of systems, apparatuses, and methods for broadcast arithmetic in a processor are described. For example, execution circuitry executes a decoded instruction to broadcast a data value from a least significant packed data element position of a first packed data source operand to a plurality of arithmetic circuits and for each packed data element position of a second packed data source operand, other than a least significant packed data element position, perform the arithmetic operation defined by the instruction on a data value from that packed data element position of the second packed data source operand and all data values from packed data element positions of the second packed data source operand that are of lesser position significance to the broadcast data value from the least significant packed data element position of the first packed data source operand, and stores a result of each arithmetic operation into a packed data element position of the packed data destination operand that corresponds to a most significant packed data element position of the second packed data source operand. ## Claims ### Claim 1 An apparatus comprising: a decoder to decode an instruction having fields for a first and a second packed data source operand, and a packed data destination operand, and execution circuitry to execute the decoded instruction to: broadcast a data value from a least significant packed data element position of the first packed data source operand to a plurality of arithmetic circuits, for each packed data element position of the second packed data source operand, other than a least significant packed data element position, perform an arithmetic operation defined by the instruction on a data value from that packed data element position of the second packed data source operand and all data values from packed data element positions of the second packed data source operand that are of lesser position significance to the broadcast data value from the least significant packed data element position of the first packed data source operand, and store a result of each arithmetic operation into a packed data element position of the packed data destination operand that corresponds to a most significant packed data element position of the second packed data source operand used in a corresponding arithmetic operation. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the first packed data source operand is a packed data register and the second packed data source operand is a memory location. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the first packed data source operand is a packed data register and the second packed data source operand is a packed data register. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein to the instruction to define the arithmetic operation in an opcode. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein arithmetic operation is one of addition, subtraction, multiplication, and division. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the execution circuitry comprises a crossbar and a plurality of adders. ### Claim 7 An method comprising: decoding an instruction having fields for a first and a second packed data source operand, and a packed data destination operand, and executing the decoded instruction to: broadcast a data value from a least significant packed data element position of the first packed data source operand to a plurality of arithmetic circuits, for each packed data element position of the second packed data source operand, other than a least significant packed data element position, perform an arithmetic operation defined by the instruction on a data value from that packed data element position of the second packed data source operand and all data values from packed data element positions of the second packed data source operand that are of lesser position significance to the broadcast data value from the least significant packed data element position of the first packed data source operand, and store a result of each arithmetic operation into a packed data element position of the packed data destination operand that corresponds to a most significant packed data element position of the second packed data source operand used in a corresponding arithmetic operation. ### Claim 8 (depends on 7) The method of claim 7, wherein the first packed data source operand is a packed data register and the second packed data source operand is a memory location. ### Claim 9 (depends on 7) The method of claim 7, wherein the first packed data source operand is a packed data register and the second packed data source operand is a packed data register. ### Claim 10 (depends on 7) The method of claim 7, wherein to the instruction to define the arithmetic operation in an opcode. ### Claim 11 (depends on 10) The method of claim 10, wherein arithmetic operation is one of addition, subtraction, multiplication, and division. ### Claim 12 (depends on 7) The method of claim 7, wherein a value of a least significant packed data element position of the packed data destination operand is unchanged by the instruction. ### Claim 13 (depends on 7) The method of claim 7, further comprising: translating the instruction from a first instruction set into an instruction of a second instruction set prior to a decode, wherein the instruction to be decoded is of the second instruction set. ### Claim 14 A non-transitory machine-readable medium storing an instruction which when executed by a processor causes the processor to perform a method, the method comprising: decoding an instruction having fields for a first and a second packed data source operand, and a packed data destination operand, and executing the decoded instruction to: broadcast a data value from a least significant packed data element position of the first packed data source operand to a plurality of arithmetic circuits, for each packed data element position of the second packed data source operand, other than a least significant packed data element position, perform an arithmetic operation defined by the instruction on a data value from that packed data element position of the second packed data source operand and all data values from packed data element positions of the second packed data source operand that are of lesser position significance to the broadcast data value from the least significant packed data element position of the first packed data source operand, and store a result of each arithmetic operation into a packed data element position of the packed data destination operand that corresponds to a most significant packed data element position of the second packed data source operand used in a corresponding arithmetic operation. ### Claim 15 (depends on 14) The non-transitory machine-readable medium of claim 14, wherein the first source packed data operand is a packed data register and the second source packed data operand is a memory location. ### Claim 16 (depends on 14) The non-transitory machine-readable medium of claim 14, wherein the first source packed data operand is a packed data register and the second source packed data operand is a packed data register. ### Claim 17 (depends on 14) The non-transitory machine-readable medium of claim 14, wherein to the instruction to define the arithmetic operation in an opcode. ### Claim 18 (depends on 17) The non-transitory machine-readable medium of claim 17, wherein arithmetic operation is one of addition, subtraction, multiplication, and division. ### Claim 19 (depends on 14) The non-transitory machine-readable medium of claim 14, wherein a value of a least significant packed data element position of the packed data destination operand is unchanged by the instruction. ### Claim 20 (depends on 14) The non-transitory machine-readable medium of claim 14, further comprising: translating the instruction from a first instruction set into an instruction of a second instruction set prior to a decode, wherein the instruction to be decoded is of the second instruction set.