# US 10,120,607 B2 · Method and apparatus for dense hyper IO digital retention > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,120,607 B2 - Document ID: US10120607B2 - Status: Granted - Kind: B2 - Application number: 15/913,907 - Filed: 2018-03-06 - Published: 2018-07-12 - Granted: 2018-11-06 - Earliest claimed: 2015-04-15 - Assignees: Formulus Black Corporation - Applicants: Symbolic IO Corporation - Inventors: Brian M. Ignomirello - Web page: https://patentgrep.com/patent/US10120607B2 ## CPC - G06F 3/064: {Management of blocks} - G06F 3/0614: {Improving the reliability of storage systems} - G06F 3/0673: {Single storage device} - H03M 7/3082: {Vector coding (for television signals, see H04N19/94)} - H03M 7/55: {Compression Theory, e.g. compression of random number, repeated compression} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract System and method to encode and decode raw data. The method to encode includes receiving a block of uncoded data, decomposing the block of uncoded data into a plurality of data vectors, mapping each of the plurality of data vectors to a bit marker; and storing the bit marker in a memory to produce an encoded representation of the uncoded data. Encoding may further include decomposing the block of uncoded data into default data and non-default data, and mapping only the non-default data. In some embodiments, bit markers may include a seed value and replication rule, or a fractalized pattern. ## Claims ### Claim 1 A specialized computer architecture computing system comprising: a computer processor in electronic communication with an internal system bus on a motherboard of the specialized computer architecture computing system; a random access memory storage in electronic communication with the computer processor through the internal system bus on the motherboard of the specialized computer architecture computing system; the computer processor configured to access through the internal system bus data stored in the random access memory storage; the computer processor configured to process all data by generating unencoded raw data blocks by concatenating together a plurality of unique unencoded data stored in the random access memory storage, and the computer processor configured to perform operations on the generated unencoded raw data blocks, wherein the computer processor utilizes bit markers to access some of the unique unencoded data stored in the random access memory storage. ### Claim 2 (depends on 1) The specialized computer architecture computing system of claim 1, wherein the computer processor accesses the bit markers from the random access memory storage and maps the bit markers to the unique unencoded data stored in the random access memory storage, and combines the unique unencoded data with a block of other uncoded data to produce a composite uncoded data block to generate the unencoded raw data blocks for the computer processor to perform operations. ### Claim 3 (depends on 1) The specialized computer architecture computing system of claim 1, wherein the generated unencoded data blocks comprises at least two instances of a unique unencoded data retrieved from the random access memory storage. ### Claim 4 (depends on 3) The specialized computer architecture computing system of claim 3, wherein the generated unencoded data blocks comprises the at least two unique encoded data retrieved from a common memory location in the random access memory storage. ### Claim 5 (depends on 1) The specialized computer architecture computing system of claim 1, wherein the random access memory storage is electronically coupled to an alternative energy source configured to provide energy when a primary energy sources fails to provide energy to the random access memory storage. ### Claim 6 (depends on 5) The specialized computer architecture computing system of claim 5, wherein the alternative energy source is a battery. ### Claim 7 (depends on 5) The specialized computer architecture computing system of claim 5, wherein the alternative energy source is a super cap. ### Claim 8 (depends on 5) The specialized computer architecture computing system of claim 5, wherein the alternative energy source is configured to supply energy to the random access storage to maintain data integrity of the random access memory storage for a period of time. ### Claim 9 (depends on 8) The specialized computer architecture computing system of claim 8, wherein the period of time is at least several months. ### Claim 10 (depends on 1) The specialized computer architecture computing system of claim 1, wherein the random access memory storage is configured to store encoded data that corresponds to an amount of uncoded data that would exceed the storage capacity of the random access memory storage. ### Claim 11 (depends on 1) The specialized computer architecture computing system of claim 1, wherein the computer processor utilizes that the random access memory storage in order to support operation of the computer processor for conventional functions. ### Claim 12 (depends on 1) The specialized computer architecture computing system of claim 1, further comprising a conventional hard drive in electronic communication with the computer processor. ### Claim 13 (depends on 1) The specialized computer architecture computing system of claim 1, wherein the generated unencoded raw data blocks represent a compound object. ### Claim 14 (depends on 1) The specialized computer architecture computing system of claim 1, wherein the generated unencoded raw data blocks represent a multi-dimensional data object. ### Claim 15 (depends on 1) The specialized computer architecture computing system of claim 1, wherein the bit markers are generated using a seed value and a replication rule. ### Claim 16 (depends on 1) The specialized computer architecture computing system of claim 1, wherein the bit markers are generated using a plurality of other bit markers and a combination rule. ### Claim 17 (depends on 1) The specialized computer architecture computing system of claim 1, wherein the bit markers are generated using fractal-based mapping. ### Claim 18 A specialized computer architecture computing system comprising: a computer processor in electronic communication with an internal system bus on a motherboard of the specialized computer architecture computing system; a random access memory storage in electronic communication with the computer processor through the internal system bus on the motherboard of the specialized computer architecture computing system; the computer processor configured to access through the internal system bus data stored in the random access memory storage; the computer processor configured to process all data by generating unencoded raw data blocks by concatenating together a plurality of unique unencoded data stored in the random access memory storage, and the computer processor configured to perform operations on the generated unencoded raw data blocks, wherein the computer processor is configured to process a first computer data file and a second computer data file, the first and second computer data files generated by the computer processor by concatenating together a plurality of unique data stored in the random access storage, wherein the first and second computer data files each comprise at least one common unique data retrieved from the random storage. ### Claim 19 (depends on 18) The specialized computer architecture computing system of claim 18, wherein the first and second computer data files each comprises the at least one common unique data retrieved from a common memory location in the random access memory storage. ### Claim 20 (depends on 18) The specialized computer architecture computing system of claim 18, wherein the random access memory storage is electronically coupled to an alternative energy source configured to provide energy when a primary energy sources fails to provide energy to the random access memory storage. ### Claim 21 (depends on 20) The specialized computer architecture computing system of claim 20, wherein the alternative energy source is a battery. ### Claim 22 (depends on 20) The specialized computer architecture computing system of claim 20, wherein the alternative energy source is a super cap. ### Claim 23 (depends on 20) The specialized computer architecture computing system of claim 20, wherein the alternative energy source is configured to supply energy to the random access storage to maintain data integrity of the random access memory storage for a period of time. ### Claim 24 (depends on 23) The specialized computer architecture computing system of claim 23, wherein the period of time is at least several months. ### Claim 25 (depends on 18) The specialized computer architecture computing system of claim 18, wherein the computer processor utilizes bit markers to access some of the unique unencoded data stored in the random access memory storage. ### Claim 26 (depends on 25) The specialized computer architecture computing system of claim 25, wherein the computer processor accesses the bit markers from the random access memory storage and maps the bit markers to the unique unencoded data stored in the random access memory storage, and combines the unique unencoded data with a block of other uncoded data to produce a composite uncoded data block to generate the unencoded raw data blocks for the computer processor to perform operations. ### Claim 27 (depends on 25) The specialized computer architecture computing system of claim 25, wherein the bit markers are generated using a seed value and a replication rule. ### Claim 28 (depends on 25) The specialized computer architecture computing system of claim 25, wherein the bit markers are generated using a plurality of other bit markers and a combination rule. ### Claim 29 (depends on 25) The specialized computer architecture computing system of claim 25, wherein the bit markers are generated using fractal-based mapping. ### Claim 30 (depends on 18) The specialized computer architecture computing system of claim 18, wherein the generated unencoded raw data blocks comprises at least two instances of a unique unencoded data retrieved from the random access memory storage. ### Claim 31 (depends on 18) The specialized computer architecture computing system of claim 18, wherein the generated unencoded raw data blocks comprises the at least two instances of a unique encoded data retrieved from a common memory location in the random access memory storage. ### Claim 32 (depends on 18) The specialized computer architecture computing system of claim 18, wherein the random access memory storage is configured to store encoded data that corresponds to an amount of uncoded data that would exceed the storage capacity of the random access memory storage. ### Claim 33 (depends on 18) The specialized computer architecture computing system of claim 18, wherein the computer processor utilizes that the random access memory storage in order to support operation of the computer processor for conventional functions. ### Claim 34 (depends on 18) The specialized computer architecture computing system of claim 18, further comprising a conventional hard drive in electronic communication with the computer processor. ### Claim 35 (depends on 18) The specialized computer architecture computing system of claim 18, wherein the generated unencoded raw data blocks represent a compound object. ### Claim 36 (depends on 18) The specialized computer architecture computing system of claim 18, wherein the generated unencoded raw data blocks represent a multi-dimensional data object.