# US 10,120,600 B2 · Persistent memory descriptor

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- Number: US 10,120,600 B2
- Document ID: US10120600B2
- Status: Granted
- Kind: B2
- Application number: 15/728,936
- Filed: 2017-10-10
- Published: 2018-03-29
- Granted: 2018-11-06
- Earliest claimed: 2015-12-08
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Aws Shallal; Collins Williams; Dan Kunkel; William Wolf
- Web page: https://patentgrep.com/patent/US10120600B2

## CPC

- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0608: {Saving storage space on storage systems}
- G06F 3/065: {Replication mechanisms}
- G06F 3/0685: {Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays}
- G06F 11/1441: {Resetting or repowering}
- G06F 11/1446: Point-in-time backing up or restoration of persistent data
- G06F 11/1448: {Management of the data involved in backup or backup restore}
- G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F 12/0868: Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G06F 11/0751: {Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06)}
- G06F 2212/1024: Latency reduction
- G06F 2212/205: Hybrid memory, e.g. using both volatile and non-volatile memory
- G06F 2212/214: Solid state disk
- G06F 2212/313: In storage device
- G06F 2212/60: Details of cache memory
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

The present invention is directed to memory systems. More specifically, embodiments of the present invention provide a memory system with a volatile memory, a persistent memory, and a controller. In a save operation, the controller copies contents of the volatile memory to the persistent memory as data units with their corresponding descriptor fields, where the descriptor fields include address information. In a restore operation, the controller copies data units from the persistent memory to their corresponding locations based on addresses stored at descriptor fields. There are other embodiments as well.

## Claims

### Claim 1

A memory controller comprising:
a processing unit configured to generate descriptor fields for memory operations occurring between a volatile memory and a persistent memory coupled to the memory controller, wherein each descriptor field corresponds to a segment of source data in the volatile memory and stores an address of the corresponding segment, the processing unit to store each segment of the source data with the corresponding descriptor field as backup data in the persistent memory and to read the backup data from the persistent memory and determine the corresponding address of each segment in the volatile memory from the corresponding descriptor field.

### Claim 2 (depends on 1)

The memory controller of claim 1, wherein each descriptor field further comprises version control information.

### Claim 3 (depends on 1)

The memory controller of claim 1, wherein each descriptor field further comprises error correction information.

### Claim 4 (depends on 1)

The memory controller of claim 1, wherein the volatile memory comprises one or more dynamic random access memory (DRAM) modules.

### Claim 5 (depends on 1)

The memory controller of claim 1, wherein the persistent memory comprises one or more flash memory modules.

### Claim 6 (depends on 1)

The memory controller of claim 1, wherein to read the backup data from the persistent memory, the processing unit to read one or more segments non-sequentially.

### Claim 7 (depends on 6)

The memory controller of claim 6, wherein the processing unit is configured to restore the one or more segments from the persistent memory to the corresponding addresses in the volatile memory based on information stored in the corresponding descriptor fields in the backup data.

### Claim 8 (depends on 7)

The memory controller of claim 7, wherein the processing unit is configured to write the one or more segments to the corresponding addresses in the volatile memory without waiting until the one or more segments are sequentially aligned.

### Claim 9

A method comprising:
initiating, by a memory controller, a save operation to copy one or more segments of source data in a volatile memory to a persistent memory;
generating a descriptor field corresponding to each segment of the source data, wherein each descriptor field stores an address of the corresponding segment in the volatile memory;
storing the one or more segments of the source data with the corresponding descriptor fields as backup data in the persistent memory; and
reading the backup data from the persistent memory to determine the addresses of the one or more segments in the volatile memory from the corresponding descriptor fields.

### Claim 10 (depends on 9)

The method of claim 9, wherein each descriptor field further comprises version control information.

### Claim 11 (depends on 9)

The method of claim 9, wherein each descriptor field further comprises error correction information.

### Claim 12 (depends on 9)

The method of claim 9, wherein the volatile memory comprises one or more dynamic random access memory (DRAM) modules.

### Claim 13 (depends on 9)

The method of claim 9, wherein the persistent memory comprises one or more flash memory modules.

### Claim 14 (depends on 9)

The method of claim 9, wherein reading the backup data from the persistent memory comprises reading the one or more segments non-sequentially.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
initiating a restore operation to copy the one or more segments from the persistent memory to the corresponding addresses in the volatile memory based on information stored in the corresponding descriptor fields in the backup data.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
writing the one or more segments to the corresponding addresses in the volatile memory without waiting until the one or more segments are sequentially aligned.

### Claim 17

A memory controller comprising:
a processing unit configured to generate descriptor fields for memory operations occurring between a dynamic random access memory (DRAM) module and a flash memory module coupled to the memory controller, wherein each descriptor field corresponds to a segment of source data in the DRAM module and stores an address of the corresponding segment, the processing unit to store each segment of the source data with the descriptor field as backup data in the flash memory module and to read the backup data from the flash memory module and determine the corresponding address of each segment in the DRAM module from the descriptor field.

### Claim 18 (depends on 17)

The memory controller of claim 17, wherein each descriptor field further comprises version control information.

### Claim 19 (depends on 17)

The memory controller of claim 17, wherein each descriptor field further comprises error correction information.

### Claim 20 (depends on 17)

The memory controller of claim 17, wherein the processing unit is configured to restore one or more non-sequential segments from the flash memory module to the corresponding addresses in the volatile memory based on information stored in the corresponding descriptor fields in the backup data without waiting until the one or more segments are sequentially aligned.