# US 10,120,590 B2 · Method for providing read data flow control or error reporting using a read data strobe

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- Number: US 10,120,590 B2
- Document ID: US10120590B2
- Status: Granted
- Kind: B2
- Application number: 15/271,527
- Filed: 2016-09-21
- Published: 2017-03-30
- Granted: 2018-11-06
- Earliest claimed: 2013-10-15
- Assignees: Cypress Semiconductor Corporation
- Applicants: Cypress Semiconductor Corporation
- Inventors: Mark Alan McClain; Qamrul Hasan; Clifford Alan Zitlaw
- Web page: https://patentgrep.com/patent/US10120590B2

## CPC

- G06F 3/0614: {Improving the reliability of storage systems}
- G06F 3/0653: {Monitoring storage devices or systems}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0665: {at area level, e.g. provisioning of virtual or logical volumes}
- G06F 3/0673: {Single storage device}
- G06F 11/0745: {in an input/output transactions management context (input/output processing in general G06F13/00)}
- G06F 11/0757: {by exceeding a time limit, i.e. time-out, e.g. watchdogs}
- G06F 11/0769: {Readable error formats, e.g. cross-platform generic formats, human understandable formats}
- G06F 11/0772: {Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Disclosed herein are system, apparatus, methods and/or combinations and sub-combinations thereof, for using a read data strobe signal received at a host device from a peripheral device to convey variable latency (flow) control or report an error in the data content read from the peripheral device. Reception of the read data strobe signal before a predetermined maximum latency time, provides variable latency control back to the host by indicating when valid data is available for capture. If the read data strobe signal is not received before expiration of a predetermined maximum latency time, the peripheral controller is indicating a read data error back to the host.

## Claims

### Claim 1

A method comprising:
programming, by a host interface of a host device, a first predetermined latency of a plurality of predetermined latencies;
counting, by the host interface, a counter value for receipt of a read data strobe signal from a peripheral device;
capturing valid data by the host interface when the counter value is not above the first predetermined latency when the read data strobe signal is received; and
sending an error response to a processing unit of the host device when the counter value is above the first predetermined latency before the read data strobe signal has been received.

### Claim 2 (depends on 1)

The method of claim 1, further comprising sending the valid data to the processing unit of the host device.

### Claim 3 (depends on 1)

The method of claim 1, wherein programming the first predetermined latency is performed by software during an idle state.

### Claim 4 (depends on 1)

The method of claim 1, wherein programming the first predetermined latency comprises setting a first number of clock pulses that corresponds to the first predetermined latency.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first predetermined latency is an initial access latency.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
programming, by the host interface, a second predetermined latency of the plurality of predetermined latencies;
wherein the second predetermined latency corresponds to a delay in reading data at a boundary between data pages in the peripheral device; and
sending a read data error to the processing unit when the read data strobe signal has not been received before expiration of the second predetermined latency.

### Claim 7

A host device comprising:
a processing unit; and
a host interface coupled to the processing unit, the host interface configured at least to:
program a first predetermined latency of a plurality of predetermined latencies;
count a counter value for receipt of a read data strobe signal from a peripheral device;
capture valid data when the counter value is not above the first predetermined latency when the read data strobe signal is received; and
send an error response to the processing unit when the counter value is above the first predetermined latency before the read data strobe signal has been received.

### Claim 8 (depends on 7)

The device of claim 7, wherein the host interface is further configured to send the valid data to the processing unit.

### Claim 9 (depends on 7)

The device of claim 7, wherein the host interface comprises software configured to program the first predetermined latency during an idle state.

### Claim 10 (depends on 7)

The device of claim 7, wherein, to program the first predetermined latency, the host interface is configured to set a first number of clock pulses that corresponds to the first predetermined latency.

### Claim 11 (depends on 7)

The device of claim 7, wherein the first predetermined latency is an initial access latency.

### Claim 12 (depends on 7)

The device of claim 7, wherein the host interface is further configured to:
program a second predetermined latency of the plurality of predetermined latencies;
wherein the second predetermined latency corresponds to a delay in reading data at a boundary between data pages in the peripheral device; and
send a read data error to the processing unit when the read data strobe signal has not been received before expiration of the second predetermined latency.

### Claim 13 (depends on 7)

The device of claim 7, wherein the device is a system-on-chip (SoC).

### Claim 14

A system comprising:
a peripheral device;
an interface bus coupled to the peripheral device; and
a host device comprising a processing unit and a host interface that is coupled to the interface bus, the host interface configured at least to:
program a first predetermined latency of a plurality of predetermined latencies;
count a counter value for receipt of a read data strobe signal from the peripheral device;
capture valid data when the counter value is not above the first predetermined latency when the read data strobe signal is received; and
send an error response to the processing unit when the counter value is above the first predetermined latency before the read data strobe signal has been received.

### Claim 15 (depends on 14)

The system of claim 14, wherein the host interface is further configured to send the valid data to the processing unit.

### Claim 16 (depends on 14)

The system of claim 14, wherein the host interface comprises software configured to program the first predetermined latency during an idle state.

### Claim 17 (depends on 14)

The system of claim 14, wherein, to program the first predetermined latency, the host interface is configured to set a first number of clock pulses that corresponds to the first predetermined latency.

### Claim 18 (depends on 14)

The system of claim 14, wherein the first predetermined latency is an initial access latency.

### Claim 19 (depends on 14)

The system of claim 14, wherein the host interface is further configured to:
program a second predetermined latency of the plurality of predetermined latencies;
wherein the second predetermined latency corresponds to a delay in reading data at a boundary between data pages in the peripheral device; and
send a read data error to the processing unit when the read data strobe signal has not been received before expiration of the second predetermined latency.

### Claim 20 (depends on 14)

The system of claim 14, wherein the peripheral device comprises flash memory and the host device is a system-on-chip (SoC).