# US 10,120,502 B2 · Array substrate, touch display panel and display apparatus containing the same, and method for driving the touch display panel

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,120,502 B2
- Document ID: US10120502B2
- Status: Granted
- Kind: B2
- Application number: 15/122,798
- Filed: 2015-12-28
- Published: 2017-06-29
- Granted: 2018-11-06
- Earliest claimed: 2015-08-13
- Assignees: Boe Technology Group Co., Ltd.; Beijing Optoelectronics Technology Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd; Beijing Boe Optoelectronics Technology Co., Ltd.
- Inventors: Shengji Yang; Xue Dong; Hailin Xue; Xiaochuan Chen; Haisheng Wang; Yingming Liu; Rui Xu; Weijie Zhao; Lei Wang; Xiaoliang Ding; Changfeng Li
- Web page: https://patentgrep.com/patent/US10120502B2

## CPC

- G06F 3/0443: {using a single layer of sensing electrodes}
- G02F 1/13338: {Input devices, e.g. touch panels}
- G02F 1/134309: {characterised by their geometrical arrangement}
- G02F 1/13458: {Terminal pads}
- G02F 1/136286: {Wiring, e.g. gate line, drain line}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- G06F 3/0412: {Digitisers structurally integrated in a display}
- G02F 1/134345: {Subdivided pixels, e.g. for grey scale or redundancy}
- G02F 2201/121: common or background
- G02F 2201/123: pixel
- G06F 3/04166: {Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving (Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184)}
- G06F 3/04184: {Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally}
- G06F 2203/04111: Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS

## Abstract

The present disclosure provides an array substrate. The array substrate includes a bottom substrate; a plurality of gate lines and a plurality of data lines arranged on the bottom substrate for defining a plurality of subpixel regions; and a plurality of common electrode pads, each common electrode pad being located in a corresponding subpixel region, wherein one or more of the common electrode pads form a self-capacitance electrode.

## Claims

### Claim 1

An array substrate, comprising:
a bottom substrate;
a plurality of gate lines and a plurality of data lines arranged on the bottom substrate for defining a plurality of subpixel regions; and
a plurality of common electrode pads, each common electrode pad being located in a corresponding subpixel region,
wherein:
two or more neighboring ones of the common electrode pads that are in a same row form at least a portion of a self-capacitance electrode,
the two or more neighboring ones of the common electrode pads in the same row are connected by a common electrode signal line through via holes,
the common electrode signal line and the plurality of gate lines are formed in a same layer, and
one of the plurality of gate lines and the common electrode signal line are arranged in a gap between two adjacent rows of the common electrode pads.

### Claim 2 (depends on 1)

The array substrate according to claim 1, wherein
the self-capacitance electrode further includes at least another one of the common electrode pads that is in a different row than the two or more neighboring ones of the common electrode pads in the same row, the at least another one of the common electrode pads in a different row is connected to the two or more neighboring ones of the common electrode pads by a connecting structure.

### Claim 3 (depends on 2)

The array substrate according to claim 2, wherein the connecting structure is located at an intersection of a gate line and a data line on the bottom substrate.

### Claim 4 (depends on 3)

The array substrate according to claim 3, wherein the connecting structure and the common electrode pads are in a same layer and made of a same material.

### Claim 5 (depends on 1)

The array substrate according to claim 1, further including an insulating layer positioned between a layer containing a common electrode pad and a layer containing a corresponding gate line.

### Claim 6 (depends on 5)

The array substrate according to claim 5, wherein: one of the via holes is formed in the insulating layer and connects a common electrode pad and a corresponding common electrode signal line.

### Claim 7 (depends on 6)

The array substrate according to claim 6, wherein the via holes have a same size; and distances between the via holes and corresponding common electrode pads are same.

### Claim 8 (depends on 1)

The array substrate according to claim 1, wherein the common electrode signal line and the plurality of gate lines are made of a same material.

### Claim 9 (depends on 1)

The array substrate according to claim 1, further comprising:
a processing unit applying common electrode signals on the common electrode pads during a display period.

### Claim 10 (depends on 1)

The array substrate according to claim 1, wherein a distance between centers of two adjacent self-capacitance electrodes is about 10 mm.

### Claim 11 (depends on 1)

The array substrate according to claim 1, wherein:
a length of the self-capacitance electrode along a row direction is about (3.85±0.15) mm; and a length of the self-capacitance electrode along a column direction is about (3.85±0.15) mm.

### Claim 12 (depends on 11)

The array substrate according to claim 11, wherein:
a ratio of the length of the self-capacitance electrode along the row direction to the length of the self-capacitance electrode along the column direction is greater than 95% and less than 105%.

### Claim 13 (depends on 1)

The array substrate according to claim 1, further including a top substrate, a plurality of thin-film transistors (TFTs) and a plurality of pixel electrodes placed in the subpixel regions between the top substrate and the bottom substrate, a gate of a TFT being connected to a gate line, a source of the TFT being connected to a data line, and a drain of the TFT being connected to a pixel electrode.

### Claim 14 (depends on 1)

A touch display panel, including one or more of the array substrates according to claim 1.

### Claim 15 (depends on 14)

The touch display panel according to claim 14, comprises a processing unit for detecting a touch motion by reading signals from the self-capacitance electrode.

### Claim 16 (depends on 14)

A display apparatus, including one or more of the display panels according to claim 14.

### Claim 17 (depends on 14)

A method for driving a touch display panel according to claim 14, comprising:
in a display period, a processing unit applying a common electrode signal on the common electrode pads; and
in a touch-sensing period, the processing unit applying a touch signal on the self-capacitance electrodes and determining a location of the touch motion based on the capacitance change on the self-capacitance electrodes, wherein the touch display panel displays a frame during the display period and the touch sensing-period.

### Claim 18 (depends on 17)

The method according to claim 17, wherein the touch signal is a periodic pulse signal.