# US 10,120,470 B2 · Semiconductor device, display device and electronic device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,120,470 B2 - Document ID: US10120470B2 - Status: Granted - Kind: B2 - Application number: 15/652,542 - Filed: 2017-07-18 - Published: 2018-01-25 - Granted: 2018-11-06 - Earliest claimed: 2016-07-22 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Semiconductor Energy Laboratory Co., Ltd. - Inventors: Yoshiyuki Kurokawa - Web page: https://patentgrep.com/patent/US10120470B2 ## CPC - G06F 3/0416: {Control or interface arrangements specially adapted for digitisers} - G06F 3/041: Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/3275: Details of drivers for data electrodes - G09G 3/3677: {suitable for active matrices only} - G09G 3/3688: {suitable for active matrices only} - G02F 1/13338: {Input devices, e.g. touch panels} - G06F 3/0412: {Digitisers structurally integrated in a display} - G06F 3/0446: {using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes} - G09G 2230/00: Details of flat display driving waveforms - G09G 2300/0426: Layout of electrodes and connections - G09G 2300/046: with an emissive area and a light-modulating area combined in one pixel - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2330/021: Power management, e.g. power saving - G09G 2330/023: using energy recovery or conservation - G09G 2354/00: Aspects of interface with display user - G09G 2360/12: Frame memory handling - G09G 2360/144: the light being ambient light - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/60: wherein the TFTs are in active matrices - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device with low power consumption is provided. The semiconductor device includes a controller, an AI controller, a frame memory, a register, and an image processing portion. The image processing portion is configured to receive image data from the frame memory and a parameter from the register, and to process the image data using the parameter. The frame memory is configured to retain the image data while power supply is stopped, and the register is configured to retain the parameter while power supply is stopped. The controller is configured to control power supply to the frame memory, the register, and the image processing portion. The AI controller is configured to predict when to switch into power gating and to provide a timing instruction to perform preparation operation for power gating. ## Claims ### Claim 1 A semiconductor device comprising: a first controller; a second controller; a frame memory; a register; and an image processing portion, wherein the frame memory is configured to store image data, wherein the image processing portion is configured to process the image data, wherein the register is configured to store a parameter for performing processing in the image processing portion, wherein the frame memory is configured to retain the image data while power supply to the frame memory is stopped, wherein the register is configured to retain the parameter while power supply to the register is stopped, wherein the first controller is configured to control the power supply to the frame memory, the power supply to the register, and power supply to the image processing portion, and wherein the second controller is configured to instruct the register in timing of performing preparation operation against stop of the power supply to the register. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, further comprising a third controller, wherein the third controller is configured to receive a first signal from a touch sensor and to generate a second signal on the basis of the first signal, wherein the second signal comprises information sensed by the touch sensor, and wherein the second controller is configured to instruct the register in timing of performing preparation operation for stop of the power supply to register on the basis of the second signal and current consumption of the frame memory. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the register comprises a scan chain register, a first register, and a second register, wherein the scan chain register comprises a third register and a fourth register, wherein an output terminal of the third register is electrically connected to an input terminal of the fourth register, wherein the first register is configured to read data stored in the third register, wherein the second register is configured to read data stored in the fourth register, wherein the data read to the first register is output to the image processing portion as the parameter and the data read to the second register is output to the image processing portion as the parameter, wherein the third register comprises a first retention circuit, wherein the fourth register comprises a second retention circuit, wherein the first retention circuit is configured to store the data stored in the third register, wherein the third register is configured to read the data stored in the first retention circuit, wherein the second retention circuit is configured to store the data stored in the fourth register, wherein the fourth register is configured to read the data stored in the second retention circuit, wherein the first retention circuit is configured to retain the stored data while the power supply to the third register is stopped, wherein the second retention circuit is configured to retain the stored data while the power supply to the fourth register is stopped, and wherein the second controller is configured to instruct the first retention circuit in timing of storing the data stored in the third register and to instruct the second retention circuit in timing of storing the data stored in the fourth register. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, further comprising a third controller, wherein the third controller is configured to receive a first signal from a touch sensor and to generate a second signal on the basis of the first signal, wherein the second signal comprises information sensed by the touch sensor, and wherein the second controller is configured to instruct the first retention circuit in timing of storing the data stored in the third register and to instruct the second retention circuit in timing of storing the data stored in the fourth register on the basis of the second signal and current consumption of the frame memory. ### Claim 5 (depends on 3) The semiconductor device according to claim 3, wherein the first retention circuit comprises a first transistor and a first capacitor, wherein the second retention circuit comprises a second transistor and a second capacitor, wherein the first transistor controls charge and discharge of the first capacitor, wherein the second transistor controls charge and discharge of the second capacitor, and wherein the first transistor and the second transistor each comprise a metal oxide in a channel formation region. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the second controller comprises a product-sum operation circuit comprising an analog memory. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein a transistor in the analog memory comprises a metal oxide in a channel formation region. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein the frame memory comprises a plurality of memory cells, wherein the memory cell comprises a third transistor and a third capacitor, wherein the third transistor controls charge and discharge of the third capacitor, and wherein the third transistor comprises a metal oxide in a channel formation region.