# US 10,120,436 B2 · Apparatuses, systems, and methods for USB high-speed chirp detection > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,120,436 B2 - Document ID: US10120436B2 - Status: Granted - Kind: B2 - Application number: 15/078,886 - Filed: 2016-03-23 - Published: 2017-09-28 - Granted: 2018-11-06 - Earliest claimed: 2016-03-23 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Chia How Low; Jia Jun Lee - Web page: https://patentgrep.com/patent/US10120436B2 ## CPC - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Methods and apparatuses relating to USB high-speed chirp detection are described. In one embodiment, a bus host transceiver circuit includes a first data path to connect to a bus device, a second data path to connect to the bus device, a squelch detection circuit with a first and a second input, and a switching circuit to couple the first data path to the first input of the squelch detection circuit separate from a first resistor and couple the second data path to the second input of the squelch detection circuit separate from a second resistor when in a first mode, and switch to a second mode to couple the first data path through the first resistor to the first input of the squelch detection circuit and couple the second data path through the second resistor to the second input of the squelch detection circuit when in a host reset period. ## Claims ### Claim 1 A bus host transceiver circuit comprising: a first data path to connect to a bus device; a second data path to connect to the bus device; a squelch detection circuit with a first input and a second input; and a switching circuit to couple the first data path to the first input of the squelch detection circuit separate from a first resistor and couple the second data path to the second input of the squelch detection circuit separate from a second resistor when in a first mode, and switch to a second mode to couple the first data path through the first resistor to the first input of the squelch detection circuit and couple the second data path through the second resistor to the second input of the squelch detection circuit when in a host reset period, wherein the first resistor comprises one of, and less than all of, a first plurality of pull-down resistors coupled to the first data path. ### Claim 2 (depends on 1) The bus host transceiver circuit of claim 1, wherein the first resistor is a plurality of, and less than all of, the first plurality of pull-down resistors coupled to the first data path. ### Claim 3 (depends on 1) The bus host transceiver circuit of claim 1, wherein the second resistor comprises one of, and less than all of, a second plurality of pull-down resistors coupled to the second data path. ### Claim 4 (depends on 1) The bus host transceiver circuit of claim 1, wherein the first resistor comprises one of, and less than all of, the first plurality of pull-down resistors coupled to the first data path to form a first voltage divider circuit and the second resistor comprises one of, and less than all of, a second plurality of pull-down resistors coupled to the second data path to form a second voltage divider circuit. ### Claim 5 (depends on 4) The bus host transceiver circuit of claim 4, wherein the first voltage divider circuit and the second voltage divider circuit decrease a differential voltage between the first data path and the second data path below an off threshold of the squelch detection circuit in the host reset period. ### Claim 6 (depends on 1) The bus host transceiver circuit of claim 1, wherein the first resistor and the second resistor decrease a differential voltage between the first data path and the second data path below an off threshold of the squelch detection circuit in the host reset period. ### Claim 7 (depends on 6) The bus host transceiver circuit of claim 6, wherein an external host controller is to drive the first data path and the second data path toward a logical zero in the host reset period. ### Claim 8 (depends on 1) The bus host transceiver circuit of claim 1, wherein a pull-up resistor of the bus device and a termination resistor are coupled to the first data path in the host reset period. ### Claim 9 A method comprising: providing a first data path and a second data path from a bus host transceiver circuit to connect to a bus device; providing a squelch detection circuit with a first input and a second input; coupling the first data path to the first input of the squelch detection circuit separate from a first resistor and coupling the second data path to the second input of the squelch detection circuit separate from a second resistor when in a first mode, the first resistor comprising one of, and less than all of, a first plurality of pull-down resistors coupled to the first data path; and switching to a second mode to couple the first data path through the first resistor to the first input of the squelch detection circuit and couple the second data path through the second resistor to the second input of the squelch detection circuit when in a host reset period. ### Claim 10 (depends on 9) The method of claim 9, wherein the first resistor is a plurality of, and less than all of, the first plurality of pull-down resistors coupled to the first data path. ### Claim 11 (depends on 9) The method of claim 9, wherein the second resistor comprises one of, and less than all of, a second plurality of pull-down resistors coupled to the second data path. ### Claim 12 (depends on 9) The method of claim 9, wherein the first resistor comprises one of, and less than all of, the first plurality of pull-down resistors coupled to the first data path to form a first voltage divider circuit and the second resistor comprises one of, and less than all of, a second plurality of pull-down resistors coupled to the second data path to form a second voltage divider circuit. ### Claim 13 (depends on 12) The method of claim 12, wherein the first voltage divider circuit and the second voltage divider circuit decrease a differential voltage between the first data path and the second data path below an off threshold of the squelch detection circuit in the host reset period. ### Claim 14 (depends on 9) The method of claim 9, wherein the first resistor and the second resistor decrease a differential voltage between the first data path and the second data path below an off threshold of the squelch detection circuit in the host reset period. ### Claim 15 (depends on 14) The method of claim 14, wherein an external host controller is to drive the first data path and the second data path toward a logical zero in the host reset period. ### Claim 16 (depends on 9) The method of claim 9, wherein a pull-up resistor of the bus device and a termination resistor of the bus host transceiver circuit are coupled to the first data path in the host reset period. ### Claim 17 A computing system comprising: a processor coupled to a system memory; and a bus host transceiver circuit comprising: a first data path to connect to a bus device, a second data path to connect to the bus device, a squelch detection circuit with a first input and a second input, and a switching circuit to couple the first data path to the first input of the squelch detection circuit separate from a first resistor and couple the second data path to the second input of the squelch detection circuit separate from a second resistor when in a first mode, and switch to a second mode to couple the first data path through the first resistor to the first input of the squelch detection circuit and couple the second data path through the second resistor to the second input of the squelch detection circuit when in a host reset period, wherein the first resistor comprises one of, and less than all of, a first plurality of pull-down resistors coupled to the first data path. ### Claim 18 (depends on 17) The computing system of claim 17, wherein the first resistor is a plurality of, but less than all of, the first plurality of pull-down resistors coupled to the first data path. ### Claim 19 (depends on 17) The computing system of claim 17, wherein the second resistor comprises one of, and less than all of, a second plurality of pull-down resistors coupled to the second data path. ### Claim 20 (depends on 17) The computing system of claim 17, wherein the first resistor comprises one of, and less than all of, the first plurality of pull-down resistors coupled to the first data path to form a first voltage divider circuit and the second resistor comprises one of, and less than all of, a second plurality of pull-down resistors coupled to the second data path to form a second voltage divider circuit. ### Claim 21 (depends on 20) The computing system of claim 20, wherein the first voltage divider circuit and the second voltage divider circuit decrease a differential voltage between the first data path and the second data path below an off threshold of the squelch detection circuit in the host reset period. ### Claim 22 (depends on 17) The computing system of claim 17, wherein the first resistor and the second resistor decrease a differential voltage between the first data path and the second data path below an off threshold of the squelch detection circuit in the host reset period. ### Claim 23 (depends on 22) The computing system of claim 22, wherein an external host controller is to drive the first data path and the second data path toward a logical zero in the host reset period. ### Claim 24 (depends on 17) The computing system of claim 17, wherein a pull-up resistor of the bus device and a termination resistor are coupled to the first data path in the host reset period.