# US 10,120,435 B2 · Multiprocessing system with peripheral power consumption control > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,120,435 B2 - Document ID: US10120435B2 - Status: Granted - Kind: B2 - Application number: 15/248,896 - Filed: 2016-08-26 - Published: 2018-03-01 - Granted: 2018-11-06 - Earliest claimed: 2016-08-26 - Assignees: NXP USA, Inc. - Applicants: Freescale Semiconductor, Inc. - Inventors: Simon J. Gallimore; Colin MacDonald; James H. Carlquist - Web page: https://patentgrep.com/patent/US10120435B2 ## CPC - G06F 1/3287: by switching off individual functional units in the computer system - G06F 1/266: {Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips} - G06F 1/3243: {Power saving in microcontroller unit} - G06F 15/163: Interprocessor communication - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract An integrated circuit device includes a peripheral control circuit configured to receive a low power intent signal from a first processor, and a first control register in the peripheral control circuit. The first control register includes a peripheral enable indicator for each processor that can use a first peripheral. Acknowledgement logic circuitry is configured to assert a first low power acknowledgement signal when the first processor issuing the low power intent signal has enabled use of the first peripheral as indicated by the peripheral enable indicator for the first processor in the first control register. ## Claims ### Claim 1 An integrated circuit device, comprising: a peripheral control circuit configured to receive a low power intent signal from a first processor; a first control register in the peripheral control circuit, wherein the first control register includes a peripheral enable indicator for each processor that can use a first peripheral; and acknowledgement logic circuitry configured to assert a first low power acknowledgement signal when the first processor issuing the low power intent signal has enabled use of the first peripheral as indicated by the peripheral enable indicator for the first processor in the first control register. ### Claim 2 (depends on 1) The integrated circuit of claim 1, further comprising: the peripheral control circuit is further configured to receive a second low power intent signal from a second processor; a second control register in the peripheral control circuit, wherein the second control register includes a peripheral enable indicator for each processor that can use a second peripheral; acknowledgement logic circuitry configured to assert a second low power acknowledgement signal when the second processor issuing the low power intent signal has enabled use of the second peripheral as indicated by the peripheral enable indicator for the second processor in the second control register. ### Claim 3 (depends on 1) The integrated circuit of claim 1, further comprising: request logic circuitry configured to assert a first low power request signal for the first peripheral when a processor issuing the low power intent signal has enabled use of the first peripheral as indicated by the peripheral enable indicator for the processor in the first control register. ### Claim 4 (depends on 3) The integrated circuit of claim 3, wherein: the request logic circuitry is configured to assert a second low power request signal for a second peripheral when a processor issuing the low power intent signal has enabled use of the second peripheral as indicated by the peripheral enable indicator for the processor in the second control register. ### Claim 5 (depends on 2) The integrated circuit of claim 2, wherein: the acknowledgement logic circuitry is further configured to assert the first low power acknowledgement signal combined for the first peripheral and the second peripheral when the first processor issuing the low power intent signal has enabled use of the first and second peripherals as indicated by the peripheral enable indicators for the first processor in the first and second control registers. ### Claim 6 (depends on 2) The integrated circuit of claim 2, wherein: the acknowledgement logic circuitry is further configured to not assert the second low power acknowledgement signal when the second processor has not enabled use of the second peripheral, even if the first processor has enabled use of the second peripheral. ### Claim 7 (depends on 2) The integrated circuit of claim 2, further comprising: request logic circuitry configured to: assert a first low power request signal for the first peripheral when the first processor issuing the low power intent signal has enabled use of the first peripheral as indicated by the peripheral enable indicator for the first processor in the first control register; and assert a second low power request signal for the second peripheral when the first processor issuing the low power intent signal has enabled use of the second peripheral as indicated by the peripheral enable indicator for the first processor in the second control register. ### Claim 8 (depends on 7) The integrated circuit of claim 7, further comprising: request logic circuitry configured to: assert the first low power request signal for the first peripheral when the second processor issuing the second low power intent signal has enabled use of the first peripheral as indicated by the peripheral enable indicator for the second processor in the first control register; and assert the second low power request signal for the second peripheral when the second processor issuing the second low power intent signal has not enabled use of the second peripheral as indicated by the peripheral enable indicator for the second processor in the second control register. ### Claim 9 (depends on 7) The integrated circuit of claim 7, further comprising: request logic circuitry configured to: assert a third low power request signal for a third peripheral when the second processor issuing the second low power intent signal has enabled use of the third peripheral as indicated by the peripheral enable indicator for the second processor in a third control register. ### Claim 10 (depends on 9) The integrated circuit of claim 9, wherein: at least two of the first, second and third low power request signals are asserted simultaneously. ### Claim 11 A method for sharing peripherals in a multiprocessor system comprising: using a first control register for a first peripheral, wherein the first control register includes an enable indicator for each processor in the multiprocessor system that can use the first peripheral; using a second control register for a second peripheral, wherein the second control register includes an enable indicator for each processor in the multiprocessor system that can use the second peripheral; generating a first low power request signal for the first peripheral when the enable indicator in the first control register for a first of the processors indicates the first of the processors has enabled use of the first peripheral, and the first of the processors has issued a first low power intent signal; and generating a second low power request signal for the second peripheral when the enable indicator in the second control register for the first or a second of the processors indicates the first or second of the processors has enabled use of the second peripheral, and the first of the processors has issued the first low power intent signal or the second of the processors has issued a second low power intent signal. ### Claim 12 (depends on 11) The method of claim 11, further comprising: generating a first low power acknowledgement signal from the first peripheral when the enable indicator in the first control register for the first of the processors indicates the first of the processors has enabled use of the first peripheral, and the first peripheral receives the first low power request signal. ### Claim 13 (depends on 12) The method of claim 12, further comprising: generating a second low power acknowledgement signal from the second peripheral when the enable indicator in the second control register for the first of the processors indicates the first of the processors has enabled use of the second peripheral, the enable indicator in the second control register for the second of the processors indicates the second of the processors has enabled use of the second peripheral, and the second peripheral receives the first and second low power request signals. ### Claim 14 (depends on 12) The method of claim 12, further comprising: generating the first and second low power request signals simultaneously. ### Claim 15 (depends on 13) The method of claim 13, further comprising: generating the first and second low power acknowledgement signals simultaneously. ### Claim 16 (depends on 12) The method of claim 12, further comprising: sending the first low power acknowledgement signal to the first of the processors when the enable indicator in the first and second control registers for the first of the processors is enabled. ### Claim 17 (depends on 13) The method of claim 13, further comprising: sending the second low power acknowledgement signal to the second of the processors when the enable indicator in the first and second control registers for the second of the processors is enabled. ### Claim 18 A multiprocessor system, comprising: a first control register for a first peripheral, wherein the first control register includes an enable indicator for each processor in the multiprocessor system that can use the first peripheral; a second control register for a second peripheral, wherein the second control register includes an enable indicator for each processor in the multiprocessor system that can use the second peripheral; acknowledgement generation circuitry configured to: generate a first low power acknowledgement signal from the first peripheral when the enable indicator in the first control register for a first of the processors indicates the first of the processors has enabled use of the first peripheral, and the first peripheral receives a first low power request signal, generate a second low power acknowledgement signal from the second peripheral when the enable indicator in the second control register for the first of the processors indicates the first of the processors has enabled use of the second peripheral, and the second peripheral receives the first low power request signal. ### Claim 19 (depends on 18) The multiprocessor system of claim 18, further comprising: request generation circuitry configured to: generate the first low power request signal for the first peripheral when the enable indicator in the first control register for the first of the processors indicates the first of the processors has enabled use of the first peripheral, and the first of the processors has issued a first low power intent signal; and generate a second low power request signal for the second peripheral when the enable indicator in the second control register for the first of the processors indicates the first of the processors has enabled use of the second peripheral, and the first of the processors has issued the first low power intent signal, or the enable indicator in the second control register for the second of the processors indicates the second of the processors has enabled use of the second peripheral, and the second of the processors has issued a second low power intent signal. ### Claim 20 (depends on 19) The multiprocessor system of claim 19, wherein: the first and second low power acknowledgement signals are generated simultaneously.