# US 10,120,434 B2 · Semiconductor device chip package with electronic switching using dedicated ground pin coupled to a virtual ground node > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,120,434 B2 - Document ID: US10120434B2 - Status: Granted - Kind: B2 - Application number: 15/154,455 - Filed: 2016-05-13 - Published: 2017-11-16 - Granted: 2018-11-06 - Earliest claimed: 2016-05-13 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Eric Pihet - Web page: https://patentgrep.com/patent/US10120434B2 ## CPC - G06F 1/3287: by switching off individual functional units in the computer system - G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C) - G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)} - G06F 13/4286: {using a handshaking protocol, e.g. RS232C link} - H03K 3/356: Bistable circuits - H03K 19/01759: {with a bidirectional operation} - H03K 19/018592: {with a bidirectional operation} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A semiconductor device is described herein. In accordance with one exemplary embodiment the semiconductor device includes a chip package, which includes at least one semiconductor chip, a dedicated ground pin, a first supply pin for receiving a first supply voltage, a second supply pin for receiving a second supply voltage, and a first input pin. The semiconductor device further includes a first circuit integrated in the semiconductor chip, wherein the first circuit is coupled to the first supply pin and to the ground pin, and a second circuit integrated in the semiconductor chip, wherein the second circuit is coupled to the first supply pin and to a virtual ground node. An electronic switch is configured to connect the virtual ground node with the first input pin dependent on the level of a first input signal. ## Claims ### Claim 1 A semiconductor device comprising: a chip package including at least one semiconductor chip, a dedicated ground pin, a first supply pin for receiving a first supply voltage, a second supply pin for receiving a second supply voltage, and a first input pin; a first circuit integrated in the semiconductor chip, the first circuit being coupled to the first supply pin and to the dedicated ground pin; a second circuit integrated in the semiconductor chip, the second circuit being coupled to the first supply pin and to a virtual ground node; and an electronic switch configured to connect the virtual ground node with the first input pin dependent on a level of a first input signal. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the first input signal is received at the first input pin, and wherein the electronic switch is configured to connect the virtual ground node with either the first input pin or the dedicated ground pin dependent on the input signal. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the electronic switch is configured to connect the virtual ground node with the first input pin when the first input signal received at the first input pin is at a low level. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the electronic switch is configured to connect the virtual ground node with the dedicated ground pin when the first input signal received at the first input pin is not at a low level. ### Claim 5 (depends on 3) The semiconductor device of claim 3, wherein the low level is substantially equal to a level present at the dedicated ground pin. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein a second supply current passes through the second circuit from the second supply pin to the virtual ground node, while the voltage drop across the second circuit substantially corresponds to the second supply voltage. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein the first input pin is a mode selection pin and the first input signal is a mode selection signal indicative of an operation mode of the semiconductor device. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the second circuit includes an output buffer circuit configured to generate an output signal at an output pin of the semiconductor chip, the output buffer circuit being supplied via the second supply pin and the virtual ground node. ### Claim 9 (depends on 8) The semiconductor device of claim 8, wherein the first input pin is a mode selection pin and the first input signal is a mode selection signal indicative of an operation mode of the semiconductor device, and wherein the virtual ground node is connected to the mode selection pin, when the mode selection signal is at a low level. ### Claim 10 (depends on 1) The semiconductor device of claim 1, wherein the first circuit includes a transmitter circuit configured to generate a first bus signal provided at at least one bus pin of the semiconductor chip. ### Claim 11 (depends on 10) The semiconductor device of claim 10, wherein the second circuit includes a receiver circuit including an output buffer circuit configured to generate an output signal at an output pin of the semiconductor chip based on a second bus signal received from the at least one bus pin. ### Claim 12 A semiconductor device comprising: a chip package including at least one semiconductor chip, a dedicated ground pin, a first supply pin for receiving a first supply voltage, a second supply pin for receiving a second supply voltage, a first input pin for receiving an input signal; a first circuit integrated in the semiconductor chip, the first circuit being coupled to the first supply pin and to the dedicated ground pin; and a second circuit integrated in the semiconductor chip, the second circuit being coupled to the first supply pin and to a virtual ground node, wherein the virtual ground node is at least temporarily connected to the first input pin, and wherein, when the virtual ground node is connected to the first input pin and the input signal received at the first input pin is at a low voltage level, a second supply current passes through the second circuit from the second supply pin to the virtual ground node, while a voltage drop across the second circuit substantially corresponds to the second supply voltage. ### Claim 13 (depends on 12) The semiconductor device of claim 12, further comprising a wired connection between the virtual ground node and the first input pin. ### Claim 14 (depends on 12) The semiconductor device of claim 12, further comprising an electronic switch configured to connect the virtual ground node either with the first input pin or with the dedicated ground pin dependent on a level of the input signal received at the input pin. ### Claim 15 (depends on 12) The semiconductor device of claim 12, wherein a second supply current passes through the second circuit from the second supply pin to the virtual ground node, while the voltage drop across the second circuit substantially corresponds to the second supply voltage. ### Claim 16 (depends on 12) The semiconductor device of claim 12, wherein the first input pin is a mode selection pin and the first input signal is a mode selection signal indicative of an operation mode of the semiconductor device. ### Claim 17 (depends on 12) The semiconductor device of claim 12, wherein the second circuit includes an output buffer circuit configured to generate an output signal at an output pin of the semiconductor chip, the output buffer circuit being supplied via the second supply pin and the virtual ground node. ### Claim 18 (depends on 17) The semiconductor device of claim 17, wherein the first input pin is a mode selection pin and the first input signal is a mode selection signal indicative of an operation mode of the semiconductor device, and wherein the virtual ground node is connected to the mode selection pin, when the mode selection signal is at a low level. ### Claim 19 (depends on 12) The semiconductor device of claim 12, wherein the first circuit includes a transmitter circuit configured to generate a first bus signal provided at at least one bus pin of the semiconductor chip. ### Claim 20 (depends on 19) The semiconductor device of claim 19, wherein the second circuit includes is a receiver circuit including an output buffer circuit that is configured to generate an output signal at an output pin of the semiconductor chip based on a second bus signal received from the at least one bus pin. ### Claim 21 A bus transceiver circuit comprising: a transmitter portion configured to receive an input data signal and to generate a corresponding first bus signal operably applied to at least one bus line; the transmitter portion of the transceiver circuit being supplied with a first supply voltage and connected to a first ground pad; a receiver portion operably coupled to the at least one bus line to receive a second bus signal and configured to generate a corresponding receive signal; and an output buffer included in the receiver portion of the transceiver circuit, the output buffer receiving the receive signal and generating a corresponding output data signal, the output buffer being supplied with a second supply voltage and connected to a second ground pad that is separate from the first ground pad. ### Claim 22 (depends on 21) The bus transceiver circuit of claim 21, wherein the receiver portion of the transceiver circuit comprises a comparator circuit receiving the second bus signal and configured to compare the second bus signal with at least one threshold; the comparator being configured to generate the receive signal being indicative of the result of the comparison. ### Claim 23 (depends on 22) The bus transceiver circuit of claim 22, wherein the comparator circuit is supplied with the first supply voltage and connected to the first ground pad. ### Claim 24 (depends on 21) The bus transceiver circuit of claim 21, wherein the bus transceiver circuit includes a first supply pin for applying the first supply voltage and a second supply pin for applying the second supply voltage. ### Claim 25 (depends on 21) The bus transceiver circuit of claim 21, wherein the bus transceiver circuit includes a first ground pin connected to the first ground pad and a second ground pin connected to the second ground pad. ### Claim 26 (depends on 21) The bus transceiver circuit of claim 21, wherein the bus transceiver circuit includes a first ground pin connected to the first ground pad and a further pin, which, at least during a normal mode of operation of the transceiver circuit, is connected to the second ground pad and supplied with a low level signal. ### Claim 27 (depends on 26) The bus transceiver circuit of claim 26, further comprising a controllable switch that is configured to connect, dependent on a voltage level present at the further pin, the second ground pad either to the first ground pin or to the further pin. ### Claim 28 (depends on 21) The bus transceiver circuit of claim 21, wherein the bus transceiver circuit is configured to operate in a sleep mode and in a normal mode, the normal mode being indicated by a specific voltage level applied to a further pin of the transceiver circuit, and wherein, at least in normal mode, the second ground pad is connected to the further pin. ### Claim 29 A transceiver device for interfacing with a data bus, the device comprising: a chip package having at least a first supply pin, a second supply pin, a ground pin, an input data pin, an output data pin, at least one bus pin for connecting at least one bus line, and a further pin; and a semiconductor chip including a receiver circuit and a transmitter circuit, wherein the transmitter circuit is configured to receive an input data signal at the input data pin and to provide a corresponding first bus signal at the at least one bus pin; the transmitter circuit being supplied with a first supply voltage applied at the first supply pin and being connected to the ground pin, wherein the receiver circuit is operably coupled to the at least one bus pin to receive a second bus signal and configured to generate a corresponding receive signal, and wherein the receiver circuit includes an output buffer that receives the receive signal and generates a corresponding output data signal at the output data pin, the output buffer being supplied with a second supply voltage applied at the second supply pin and being connected to a circuit node, which is configured to be connected to the further pin. ### Claim 30 (depends on 29) The transceiver device of claim 29, wherein at least during a normal operation of the device the circuit node is connected to the further pin that is operably supplied with a low level signal during normal operation. ### Claim 31 A method executed in a semiconductor device that comprises: a chip package including at least one semiconductor chip, a dedicated ground pin, a first supply pin for receiving a first supply voltage, a second supply pin for receiving a second supply voltage, and a first input pin; a first circuit integrated in the semiconductor chip, the first circuit being coupled to the first supply pin and to the dedicated ground pin; and a second circuit integrated in the semiconductor chip, the second circuit being coupled to the first supply pin and to a virtual ground node; wherein the method comprises: receiving a first input signal at the first input pin; and connecting, using an electronic switch, the virtual ground node with the first input pin dependent on a level of a first input signal. ### Claim 32 (depends on 31) The method of claim 31, further comprising: receiving the first input signal at the first input pin; and connecting, using the electronic switch, the virtual ground node either with the first input pin or with the dedicated ground pin dependent on the level of the first input signal. ### Claim 33 (depends on 31) The method of claim 31, wherein the level of the first input signal is a voltage level of the first input signal, and wherein connecting the virtual ground node comprises: evaluating the voltage level of the first input signal; if the voltage level of the first input signal is a low level: connecting the virtual ground node with the first input pin; and if the voltage level of the first input signal is not a low level: connecting the virtual ground node with the dedicated ground pin. ### Claim 34 A system comprising: a controller device comprising an output pin; and a semiconductor device, comprising: a chip package including at least one semiconductor chip, a dedicated ground pin, a first supply pin for receiving a first supply voltage, a second supply pin for receiving a second supply voltage, a first input pin connected to the output pin of the controller device; a first circuit integrated in the semiconductor chip, the first circuit being coupled to the first supply pin and to the dedicated ground pin; a second circuit integrated in the semiconductor chip, the second circuit being coupled to the first supply pin and to a virtual ground node; and an electronic switch configured to connect the virtual ground node with the first input pin dependent on a level of an input signal. ### Claim 35 (depends on 34) The system of claim 34, wherein the first input pin connected to the output pin of the controller device is configured to receive the input signal from the controller device.