# US 10,120,408 B2 · Event controlled clock switching > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,120,408 B2 - Document ID: US10120408B2 - Status: Granted - Kind: B2 - Application number: 14/870,396 - Filed: 2015-09-30 - Published: 2017-03-30 - Granted: 2018-11-06 - Earliest claimed: 2015-09-30 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Joerg Harald Hans Jochen Schreiner; Marcus Herzog - Web page: https://patentgrep.com/patent/US10120408B2 ## CPC - G06F 1/08: Clock generators with changeable or programmable clock frequency - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A system and method for controlling clock generation. A system includes a processor configured to execute instructions retrieved from memory, and a clock generation system coupled to the processor. The clock generation system is configured to generate a clock signal that the processor applies to execute the instructions. The clock generation system includes a plurality of configuration registers and selection circuitry. Each of the configuration registers includes fields that control a frequency of the clock signal. The selection circuitry selects which of the plurality of configuration registers determines the frequency at a given time. ## Claims ### Claim 1 A system, comprising: a processor configured to execute instructions retrieved from memory; a clock generation system coupled to the processor and configured to generate a clock signal for the processor to apply to execute the instructions, the clock generation system comprising: a plurality of configuration registers, each of the configuration registers comprising fields to control a frequency of the clock signal; event association logic to receive an event signal that indicates an occurrence of an event within the system and to output a selection control signal selected from a plurality of selection control signals responsive to the receiving of the event signal indicating the occurrence of the event, wherein the event association logic includes a plurality of registers, wherein each of the plurality of registers of the event association logic stores initialization data that associates the register with a respective one of the plurality of selection control signals; and selection circuitry to receive the selected selection control signal and, responsive to the selected selection control signal, to associate a respective one of the configuration registers with the event occurring within the system by selecting which of the plurality of configuration registers determines the frequency of the clock signal; wherein the clock generation system is configured to change the frequency of the clock signal during operation of the processor, and irrespective of instructions executed by the processor, and the initialization data stored in the plurality of registers of the event association logic is provided to the event association logic by the processor; wherein events associated with the configuration registers include: an interrupt to be serviced by the processor; a completion of an interrupt service; a change in a level of a signal at an input terminal of the processor; and a change in a mode of the processor responsive to the processor executing an instruction; and wherein the plurality of selection control signals includes: a first selection control signal corresponding to the interrupt to be serviced by the processor; a second selection control signal corresponding to the completion of the interrupt service; a third selection control signal corresponding to the change in the level of the signal at the input terminal of the processor; and a fourth selection control signal corresponding to the change in the mode of the processor responsive to the processor executing the instruction. ### Claim 2 (depends on 1) The system of claim 1, wherein occurrence of the event causes the selection circuitry to change the frequency of the clock signal by changing which of the configuration registers determines the frequency of the clock signal. ### Claim 3 (depends on 1) The system of claim 1, wherein the change in the mode of the processor in response to the processor executing the instruction is a change in a power mode of the processor. ### Claim 4 (depends on 1) The system of claim 1, wherein the fields of each of the configuration registers is configured to: select a clock source from a plurality of clock sources to provide a clock for generation of the clock signal; and provide a divisor value to be applied to divide the clock for generation of the clock signal. ### Claim 5 (depends on 4) The system of claim 4, wherein the clock sources comprise a phase locked loop output, a crystal oscillator output, and an R-C oscillator output. ### Claim 6 (depends on 4) The system of claim 4, wherein the fields of each of the configuration registers are configured to selectively enable and disable each of the plurality of clock sources. ### Claim 7 (depends on 1) The system of claim 1, wherein the clock generation system includes clock source circuitry to receive information contained in the configuration register selected by the selection circuitry as clock source control signals and to generate the clock signal in response thereto, the clock source circuitry including: a high frequency oscillator; a low frequency oscillator; a reference oscillator; a phase locked loop; a first divider circuit having a first output; and a second divider circuit having a second output. ### Claim 8 (depends on 7) The system of claim 7, wherein the clock signal is one of the first output or the second output. ### Claim 9 (depends on 7) The system of claim 7, wherein the clock source control signals are supplied to each of the high frequency oscillator, the low frequency oscillator, the reference oscillator, the phase locked loop, the first divider circuit, and second divider circuit. ### Claim 10 (depends on 9) The system of claim 9, wherein the clock source circuitry includes a selector having: a plurality of inputs each coupled to a respective one of the high frequency oscillator, the low frequency oscillator, the reference oscillator, and the phase locked loop; and an output coupled in common to the first divider circuit and the second divider circuit. ### Claim 11 (depends on 10) The system of claim 10, wherein the information contained in the configuration register selected by the selection circuitry includes: a first field containing a first value that selectively enables or disables the high frequency oscillator; a second field containing a second value that selectively enables or disables the low frequency oscillator; a third field containing a third value that selectively enables or disables the reference oscillator; a fourth field containing a fourth value that selectively enables or disables the phase locked loop; a fifth field containing a fifth value that is supplied to the selector as a control signal to select one of the plurality of inputs of the selector to supply at the output of the selector; a sixth field containing a sixth value specifying a divisor for the first divider circuit; and a seventh field containing a seventh value specifying a divisor for the second divider circuit. ### Claim 12 An electronic data processing system, comprising: a memory to store instructions; a processor to execute the instructions retrieved from the memory; a clock generation system coupled to the processor and configured to generate at least one clock signal for the processor to apply to execute the instructions, the clock generation system comprising: a plurality of configuration registers, each of the configuration registers comprising fields to control a frequency of the at least one clock signal and each of the configuration registers being associated with a respective one of a plurality of events; event association logic to receive an event signal that indicates an occurrence of one of the plurality of events within the system and, in response to the received event signal, output a selection control signal corresponding to the occurring event, the selection control signal being selected from a plurality of selection control signals; selection circuitry having a plurality of inputs each coupled to a respective one of the configuration registers, wherein the selection circuitry is configured to receive the selection control signal and to select one of the configuration registers corresponding to the occurring event; and clock source circuitry to receive from the selection circuitry information contained in the selected configuration register and to output the at least one clock signal having a frequency determined by the information contained in the selected configuration register; wherein events associated with the configuration registers include an interrupt to be serviced by the processor, a completion of an interrupt service, a change in a level of a signal at an input terminal of the processor, and a change in a mode of the processor responsive to the processor executing an instruction; and wherein the plurality of selection control signals includes a first selection control signal corresponding to the interrupt to be serviced by the processor, a second selection control signal corresponding to the completion of the interrupt service, a third selection control signal corresponding to the change in the level of the signal at the input terminal of the processor, and a fourth selection control signal corresponding to the change in the mode of the processor responsive to the processor executing the instruction. ### Claim 13 (depends on 12) The electronic data processing system of claim 12, wherein the event association logic includes a plurality of registers, wherein each of the plurality of registers of the event association logic stores initialization data that associates the register with a respective one of the plurality of selection control signals. ### Claim 14 (depends on 12) The electronic data processing system of claim 12, wherein the clock generation system is configured to change the frequency of the clock signal during operation of the processor and irrespective of instructions executed by the processor. ### Claim 15 (depends on 12) The electronic data processing system of claim 12, wherein the clock source circuitry includes: a high frequency oscillator; a low frequency oscillator; a reference oscillator; a phase locked loop; a first divider circuit having a first output; and a second divider circuit having a second output. ### Claim 16 (depends on 15) The electronic data processing system of claim 15, wherein the at least one clock signal includes a first clock signal and a second clock signal, the first clock signal being the first output and the second clock signal being the second output. ### Claim 17 (depends on 15) The electronic data processing system of claim 15, wherein the clock source control signals are supplied to each of the high frequency oscillator, the low frequency oscillator, the reference oscillator, the phase locked loop, the first divider circuit, and second divider circuit. ### Claim 18 (depends on 17) The electronic data processing system of claim 17, wherein the clock source circuitry includes a selector having: a plurality of inputs each coupled to a respective one of the high frequency oscillator, the low frequency oscillator, the reference oscillator, and the phase locked loop; and an output coupled in common to an input of the first divider circuit and to an input of the second divider circuit. ### Claim 19 (depends on 18) The electronic data processing system of claim 18, wherein the information contained in the configuration register selected by the selection circuitry includes: a first field containing a first value that selectively enables or disables the high frequency oscillator; a second field containing a second value that selectively enables or disables the low frequency oscillator; a third field containing a third value that selectively enables or disables the reference oscillator; a fourth field containing a fourth value that selectively enables or disables the phase locked loop; a fifth field containing a fifth value that is supplied to the selector as a control signal to select one of the plurality of inputs of the selector to supply at the output of the selector; a sixth field containing a sixth value specifying a divisor for the first divider circuit; and a seventh field containing a seventh value specifying a divisor for the second divider circuit. ### Claim 20 (depends on 12) The electronic data processing system of claim 12, wherein the electronic data processing system is a microcontroller.