# US 10,120,265 B2 · Photonic crystal all-optical multistep-delay OR-transformation logic gate

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- Number: US 10,120,265 B2
- Document ID: US10120265B2
- Status: Granted
- Kind: B2
- Application number: 15/626,261
- Filed: 2017-06-19
- Published: 2017-10-12
- Granted: 2018-11-06
- Earliest claimed: 2014-12-19
- Assignees: Zhengbiao Ouyang
- Applicants: Zhengbiao Ouyang
- Inventors: Zhengbiao Ouyang; Quanqiang Yu
- Web page: https://patentgrep.com/patent/US10120265B2

## CPC

- G02F 3/00: Optical logic elements; Optical bistable devices
- G02B 6/1225: {comprising photonic band-gap structures or photonic lattices}
- G02B 6/125: Bends, branchings or intersections
- G02F 2201/06: integrated waveguide
- G02F 2202/32: Photonic crystals
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02B: OPTICAL ELEMENTS, SYSTEMS OR APPARATUS

## Abstract

A PhC all-optical multistep-delay OR-transformation logic gate includes an optical switch unit having a first intermediate-signal output port, a PhC structure unit having a first intermediate-signal input port connected with the first intermediate-signal output port, a reference-light source connected with the reference-light input port of the optical switch unit, a wave absorbing load, a flip-flop unit, and a memory or delayer having an input port connected with a first logic signal and an output port connected with the delay-signal input port of an optical switch unit whose logic-signal input port is connected with a second logic signal; a second intermediate-signal input port of the PhC structure unit is connected with the second intermediate-signal output port of said optical switch unit; a third intermediate-signal output port of the optical switch unit is connected with the wave absorbing load; a clock control-signal is input through the input port of a two-branch waveguide.

## Claims

### Claim 1

A PhC all-optical multistep-delay OR-transformation logic gate, wherein said PhC all-optical multistep-delay OR-transformation logic gate comprising:
an optical switch unit, a PhC structure unit, a reference-light source, wave absorbing load, a D-type flip-flop unit and a memory or delayer; an input port of a memory or delayer is connected with a first logic-signal X1, and the output port of the memory or delayer is connected with the delay-signal input port of an optical switch unit; a logic-signal input port of said optical switch unit is connected with a second logic-signal X2; said reference-light source is connected with the reference-light input port of said optical switch unit; a first intermediate-signal input port of said PhC structure unit is connected with the first intermediate-signal output port of said optical switch unit; the second intermediate-signal input port of said PhC structure unit is connected with the second intermediate-signal output port of said optical switch unit; and the third intermediate-signal output port of said optical switch unit is connected with the wave absorbing load; a clock control-signal CP is input through the input port of a two-branch waveguide, one port of a two-branch waveguide is connected with a clock-signal CP input port of said optical switch unit, and another port of a two-branch waveguide is connected with said clock-signal input port of said D-type flip-flop unit; the D-signal input port of said D-type flip-flop unit is connected with the signal-output port of said PC structure unit.

### Claim 2 (depends on 1)

The PhC all-optical multistep-delay OR-transformation logic gate according to claim 1, wherein said the optical switch unit is a 3×3 optical selector switch, and includes a clock-signal CP input port, two signal-input ports, a reference-light input port and three intermediate-signal output ports; and the two signal-input ports are respectively delay-signal input port and logic-signal input port, and said three intermediate-signal output ports are respectively the first intermediate-signal output port, the second intermediate-signal output port and the third intermediate-signal output port.

### Claim 3 (depends on 1)

The PhC all-optical multistep-delay OR-transformation logic gate according to claim 1, wherein said PhC structure unit is a 2D-PhC cross-waveguide nonlinear cavity and is a 2D-PhC cross intersected waveguide four-port network formed by high-refractive-index, the four-port network has a four-port PhC structure, a left port is said first intermediate-signal input port, a lower port is said second intermediate-signal input port, an upper port is a signal-output port, and a right port is an idle port; two mutually-orthogonal quasi-one-dimensional (1D) PhC structures are placed in two waveguide directions crossed at a center of said cross waveguide, a dielectric pillar is arranged in a middle of said cross waveguide, said dielectric pillar is made of a nonlinear material, and a cross section of said dielectric pillar is square, polygonal, circular or oval; and the dielectric constant of a rectangular linear pillar clinging to the central nonlinear pillar and close to the signal-output port is equal to that of said central nonlinear pillar under low-light-power conditions; and said quasi-1DPhC structures and said dielectric pillar constitute a waveguide defect cavity.

### Claim 4 (depends on 1)

The PhC all-optical multistep-delay OR-transformation logic gate according to claim 1, wherein said D-type flip-flop unit includes a clock-signal input port, a D-signal input port and a system output port; an input signal at said D-signal input port in said D-type flip-flop unit is equal to the output signal at said output port in said PhC structure unit.

### Claim 5 (depends on 1)

The PhC all-optical multistep-delay OR-transformation logic gate according to claim 1, wherein said memory includes an input port and an output port; and said output signal of the memory is the input signal input into said memory before the k steps; the delayer includes an input port and an output port; and said output signal of the delayer has k-step delay relative to the input signal thereof.

### Claim 6 (depends on 1)

The PhC all-optical multistep-delay OR-transformation logic gate according to claim 1, wherein said memory or delayer provides the one of k-step delay.

### Claim 7 (depends on 1)

The PhC all-optical multistep-delay OR-transformation logic gate according to claim 1, wherein said 2D-PhC is of a (2k+1)×(2k+1) structure, where k is an integer more than or equal to 3.

### Claim 8 (depends on 1)

The PhC all-optical multistep-delay OR-transformation logic gate according to claim 1, wherein said cross section of the high-refractive-index dielectric pillar of said 2D-PhC is circular, oval, triangular or polygonal.

### Claim 9 (depends on 1)

The PhC all-optical multistep-delay OR-transformation logic gate according to claim 1, wherein a background filling material for the 2D-PhC is air or a different low-refractive-index medium with a refractive index less than 1.4.

### Claim 10 (depends on 1)

The PhC all-optical multistep-delay OR-transformation logic gate according to claim 1, wherein said refractive index of said dielectric pillar in the quasi-1D PhC of said cross waveguide is 3.4 or a different value more than 2, and the cross section of said dielectric pillar in said quasi-1D PhC is rectangular, polygonal, circular or oval.