# US 10,120,256 B2 · Preparation method for thin film transistor, preparation method for array substrate, array substrate, and display apparatus

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- Number: US 10,120,256 B2
- Document ID: US10120256B2
- Status: Granted
- Kind: B2
- Application number: 15/521,471
- Filed: 2015-12-31
- Published: 2017-11-16
- Granted: 2018-11-06
- Earliest claimed: 2015-08-14
- Assignees: Boe Technology Group Co., Ltd.; Ordos Yuansheng Optoelectronics Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.; Ordos Yuansheng Optoelectronics Co., Ltd.
- Inventors: Lulu Ye; Huafeng Liu; Jingping Lv; Lei Yang; Meng Yang; Kai Zhang; Chao Wang; Chaochao Sun; Shengwei Zhao
- Web page: https://patentgrep.com/patent/US10120256B2

## CPC

- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- G02F 1/134363: {for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]}
- G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer}
- H10D 84/01: Manufacture or treatment
- H10D 86/01: Manufacture or treatment
- H10D 86/021: {of multiple TFTs}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/0223: {comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials}
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/0251: {characterised by increasing the uniformity of device parameters}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10K 59/1213: {the pixel elements being TFTs}
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

Preparation method for a thin film transistor, preparation method for an array substrate, an array substrate, and a display apparatus are provided. The preparation method for a thin film transistor includes: forming, on a pattern of a semiconductor layer, a first photoresist pattern including a photoresist with two different thicknesses, and performing a heavily-doped ion implantation process on the pattern of the semiconductor layer by using the first photoresist pattern as a barrier mask; ashing the first photoresist pattern to remove the photoresist with a second thickness and to thin the photoresist with a first thickness, so as to form a second photoresist pattern; and performing a lightly-doped ion implantation process on the pattern of the semiconductor layer by using the second photoresist pattern as a barrier mask.

## Claims

### Claim 1

A method for manufacturing a thin-film transistor (TFT), comprising:
forming a pattern of a semiconductor layer on a base substrate;
forming an interlayer dielectric layer on the pattern of the semiconductor layer;
forming a first photoresist pattern on the interlayer dielectric layer, the first photoresist pattern including first-thickness photoresist and second-thickness photoresist; the first-thickness photoresist corresponding to an area, at which a channel region is to be formed, in the pattern of the semiconductor layer; the second-thickness photoresist corresponding to areas, at which a source lightly doped region and a drain lightly doped region are to be formed, in the pattern of the semiconductor layer; the first-thickness photoresist has a thickness greater than that of the second-thickness photoresist;
performing heavily doped ion implantation on the pattern of the semiconductor layer by taking the first photoresist pattern as a barrier mask, and forming patterns of a source heavily doped region and a drain heavily doped region;
performing ashing treatment on the first photoresist pattern, so as to remove the second-thickness photoresist and reduce the thickness of the first-thickness photoresist, and form a second photoresist pattern;
performing lightly doped ion implantation on the pattern of the semiconductor layer by taking the second photoresist pattern as a barrier mask, and forming patterns of the channel region, the source lightly doped region and the drain lightly doped region; and
removing the second photoresist pattern.

### Claim 2 (depends on 1)

The method for manufacturing the TFT according to claim 1, wherein a source of the TFT is formed by the source lightly doped region and the source heavily doped region; a drain of the TFT is formed by the drain lightly doped region and the drain heavily doped region; and the source and the drain has an interval therebetween so as to define the channel region.

### Claim 3 (depends on 1)

The method for manufacturing the TFT according to claim 1, wherein the second-thickness photoresist is located on both sides of the first-thickness photoresist.

### Claim 4 (depends on 1)

The method for manufacturing the TFT according to claim 1, wherein forming the first photoresist pattern includes:
forming a photoresist film, performing exposure and development on the photoresist film via a multi-tone mask, and forming the first photoresist pattern, the first photoresist pattern including a photoresist-completely-retained region and photoresist-partially-retained regions; the photoresist-completely-retained region corresponding to the area, at which the channel region is to be formed, in the pattern of the semiconductor layer; and the photoresist-partially-retained regions corresponding to the areas, at which the source lightly doped region and the drain lightly doped region are to be formed, in the pattern of the semiconductor layer.

### Claim 5 (depends on 1)

The method for manufacturing the TFT according to claim 1, wherein the multi-tone mask includes any one of a half-tone mask and a gray-tone mask.

### Claim 6 (depends on 1)

The method for manufacturing the TFT according to claim 1, further comprising forming a pattern of a gate electrode, wherein the pattern of the gate electrode is formed before forming of the pattern of the semiconductor layer.

### Claim 7 (depends on 1)

The method for manufacturing the TFT according to claim 1, further comprising forming a buffer layer, wherein the buffer layer is disposed between the pattern of the gate electrode and the pattern of the semiconductor layer.

### Claim 8 (depends on 1)

The method for manufacturing the TFT according to claim 1, wherein the material of the semiconductor layer includes polycrystalline silicon (poly-Si).

### Claim 9 (depends on 1)

The method for manufacturing the TFT according to claim 1, wherein n-type doping is performed in the heavily doped ion implantation process and the lightly doped ion implantation process.

### Claim 10 (depends on 9)

The method for manufacturing the TFT according to claim 9, wherein doped ions are phosphorus ions.

### Claim 11 (depends on 1)

A method for manufacturing an array substrate, comprising the method for manufacturing the TFT according to claim 1.

### Claim 12 (depends on 11)

The method for manufacturing the array substrate according to claim 11, wherein a source of the TFT is formed by the source lightly doped region and the source heavily doped region; a drain of the TFT is formed by the drain lightly doped region and the drain heavily doped region; and the source and the drain has an interval therebetween so as to define the channel region.

### Claim 13 (depends on 11)

The method for manufacturing the array substrate according to claim 11, wherein the second-thickness photoresist is located on both sides of the first-thickness photoresist.

### Claim 14 (depends on 11)

The method for manufacturing the array substrate according to claim 11, wherein forming the first photoresist pattern includes:
forming a photoresist film, performing exposure and development on the photoresist film via a multi-tone mask, and forming the first photoresist pattern, the first photoresist pattern including a photoresist-completely-retained region and photoresist-partially-retained regions; the photoresist-completely-retained region corresponding to the area, at which the channel region is to be formed, in the pattern of the semiconductor layer; and the photoresist-partially-retained regions corresponding to the areas, at which the source lightly doped region and the drain lightly doped region are to be formed, in the pattern of the semiconductor layer.

### Claim 15 (depends on 11)

The method for manufacturing the array substrate according to claim 11, wherein the multi-tone mask includes any one of a half-tone mask and a gray-tone mask.