# US 10,120,253 B2 · Display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,120,253 B2 - Document ID: US10120253B2 - Status: Granted - Kind: B2 - Application number: 15/834,388 - Filed: 2017-12-07 - Published: 2018-04-12 - Granted: 2018-11-06 - Earliest claimed: 2014-09-05 - Assignees: Japan Display Inc. - Applicants: Japan Display Inc. - Inventors: Motoharu Miyamoto; Teppei Yamada; Yasuhiro Kanaya - Web page: https://patentgrep.com/patent/US10120253B2 ## CPC - G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer} - G02F 1/136286: {Wiring, e.g. gate line, drain line} - H10D 86/471: {having different architectures, e.g. having both top-gate and bottom-gate TFTs} - H10D 86/60: wherein the TFTs are in active matrices - G02F 1/1362: Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)} - G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} - H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer} - H10D 86/441: {Interconnections, e.g. scanning lines} - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A display device is provided with a pixel and a dummy pixel including a gate line and a signal line. The dummy pixel includes the gate line and a dummy semiconductor layer crossing the gate line through an insulating layer. The dummy semiconductor layer is electrically separated from the dummy semiconductor layer of the dummy pixel adjacent in the Y direction dummy pixel. The dummy pixel further includes a dummy signal line extending in the Y direction. The dummy signal line is connected to the dummy semiconductor layer through a plurality of contact holes. The contact holes are arranged with the gate line interposed between them in plan view. ## Claims ### Claim 1 A display device comprising: a display area including a plurality of first pixels; and an outside display area including a plurality of second pixels, which is arranged outside of the display area, wherein the first pixel includes; a thin film transistor including an inside display area semiconductor layer, a gate line connected to a gate electrode of the thin film transistor, and a signal line connected to a drain electrode of the thin film transistor, wherein the second pixel includes; the gate line, a plurality of the outside display area semiconductor layer crossing the gate line, and a plurality of outside display area signal line crossing the gate line, and wherein the outside display area signal lines are arranged on the outside display area semiconductor layer, an insulating layer is formed between the outside display area signal lines and the outside display area semiconductor layer, the outside display area signal line is connected to the outside display area semiconductor layer through a plurality of a contact holes, the outside display area semiconductor layer includes; a first outside display area semiconductor layer in which the contact holes are arranged one by one with the gate line interposed therebetween in plan view, and a second outside display area semiconductor layer includes in which the contact holes are arranged on one side with the gate line interposed therebetween in plan view. ### Claim 2 (depends on 1) The display device according to claim 1, wherein a plurality of the second pixels are arranged with respect to one gate line. ### Claim 3 (depends on 1) The display device according to claim 1, wherein the first outside area semiconductor layer is formed in the same layer with the same width as the first semiconductor layer in an intersection portion with the gate line. ### Claim 4 (depends on 1) The display device according to claim 1, wherein an interval of the outside display area signal lines is narrower than the interval of the signal lines. ### Claim 5 (depends on 1) The display device according to claim 1, wherein the outside display area signal line is formed in the same layer with the same width as the signal line. ### Claim 6 (depends on 1) The display device according to claim 1, wherein the outside display area signal line is formed in the same layer as the signal line with a larger width than the width of the signal line. ### Claim 7 (depends on 1) The display device according to claim 1, wherein the second outside display area semiconductor layer is formed in the same layer as the inside display area semiconductor layer with a larger width than the width of the inside display area semiconductor layer in the intersection portion with the gate line. ### Claim 8 (depends on 1) The display device according to claim 1, wherein the inside display area semiconductor and the first and the second outside display area semiconductor layers are formed in a lower layer than the gate line. ### Claim 9 (depends on 1) The display device according to claim 1, wherein the inside display area semiconductor and the first and the second semiconductor layers are formed in an upper layer than the gate line. ### Claim 10 (depends on 1) The display device according to claim 1, wherein the inside display area semiconductor and the first and the second semiconductor layers are formed of low-temperature polycrystalline silicon or amorphous silicon. ### Claim 11 (depends on 1) The display device according to claim 1, wherein the first pixel includes a pixel electrode and a common electrode.