# US 10,120,252 B2 · Array substrate and manufacturing method thereof

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- Number: US 10,120,252 B2
- Document ID: US10120252B2
- Status: Granted
- Kind: B2
- Application number: 15/123,064
- Filed: 2016-04-28
- Published: 2018-03-29
- Granted: 2018-11-06
- Earliest claimed: 2016-04-08
- Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Applicants: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Inventors: Hui Xia; Tienchun Huang
- Web page: https://patentgrep.com/patent/US10120252B2

## CPC

- G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer}
- G02F 1/1335: Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F 1/1343: Electrodes {(reflective electrodes G02F1/133553)}
- G02F 1/136277: {formed on a semiconductor substrate, e.g. of silicon}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- H10D 84/01: Manufacture or treatment
- H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D 86/01: Manufacture or treatment
- H10D 86/021: {of multiple TFTs}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/0241: {using liquid deposition, e.g. printing}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/60: wherein the TFTs are in active matrices
- G02F 1/133357: {Planarisation layers}
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An array substrate and a manufacturing method thereof are disclosed. The array substrate includes: a glass substrate; a gate electrode; a first insulating layer; a semiconductor layer; a planarization layer mounted on the first insulating layer; a source electrode and a drain electrode; a pixel electrode layer mounted on the planarization layer and the drain electrode; a second insulating layer mounted on the planarization layer, the semiconductor layer, the source electrode and the drain electrode. The array substrate can prevent bubbles from forming at through holes and thereby increasing aperture ratio. The planarization layer further increases distances between the source electrode, the drain electrode and the gate electrode, which enhances antistatic ability.

## Claims

### Claim 1

An array substrate, comprising:
a glass substrate;
a gate electrode mounted on the glass substrate;
a first insulating layer deposited on the glass substrate and the gate electrode;
a semiconductor layer mounted on the first insulating layer and positioned on a top of the gate electrode;
a planarization layer mounted on the first insulating layer;
a source electrode mounted on the planarization layer and the semiconductor layer;
a drain electrode mounted on the planarization layer and the semiconductor layer;
a pixel electrode layer mounted on the planarization layer and the drain electrode; and
a second insulating layer mounted on the planarization layer, the semiconductor layer, the source electrode and the drain electrode,wherein the drain electrode has a side surface which is away from one side of the source electrode and is inclined towards the source electrode, and the pixel electrode layer covers the side surface.

### Claim 2 (depends on 1)

The array substrate as claimed in claim 1, wherein the semiconductor layer includes:
an amorphous silicon layer deposited on the first insulating layer; and
a doped semiconductor layer mounted on the amorphous silicon layer.

### Claim 3 (depends on 1)

The array substrate as claimed in claim 1, wherein the first insulating layer is made of silicon nitride and/or silicon dioxide.

### Claim 4 (depends on 1)

The array substrate as claimed in claim 1, wherein the second insulating layer is made of silicon nitride and/or silicon dioxide.

### Claim 5 (depends on 1)

The array substrate as claimed in claim 1, wherein the planarization layer is formed by 3D printing using nano-powder material or liquid insulating material.

### Claim 6

An array substrate, comprising:
a glass substrate;
a gate electrode mounted on the glass substrate;
a first insulating layer deposited on the glass substrate and the gate electrode;
a semiconductor layer mounted on the first insulating layer and positioned on a top of the gate electrode;
a planarization layer mounted on the first insulating layer;
a source electrode mounted on the planarization layer and the semiconductor layer;
a drain electrode mounted on the planarization layer and the semiconductor layer;
a pixel electrode layer mounted on the planarization layer and the drain electrode;
a second insulating layer mounted on the planarization layer, the semiconductor layer, the source electrode and the drain electrode; wherein the semiconductor layer includes:
an amorphous silicon layer deposited on the first insulating layer; and
a doped semiconductor layer mounted on the amorphous silicon layer;
the drain electrode has a side surface which is away from one side of the source electrode and is inclined towards the source electrode, and the pixel electrode layer covers the side surface.

### Claim 7

A manufacturing method of an array substrate, comprising steps of:
mounting a gate electrode on a glass substrate;
depositing a first insulating layer on the glass substrate and the gate electrode;
depositing a semiconductor layer on the first insulating layer, wherein the semiconductor layer is disposed on a top of the gate electrode;
mounting a pianarization layer on the first insulating layer;
mounting a source electrode on the planarization layer and the semiconductor layer;
mounting a drain electrode on the planarization layer and the semiconductor layer;
mounting a pixel electrode layer on the planarization layer and the drain electrode; and
depositing a second insulating layer on the planarization layer, the semiconductor layer, the source electrode and the drain electrode, wherein the drain electrode has a side surface which is away from one side of the source electrode and is inclined towards the source electrode, and the pixel electrode layer covers the side surface.

### Claim 8 (depends on 7)

The manufacturing method as claimed in claim 7, wherein the planarization layer is formed by 3D printing using nano-powder material or liquid insulating material.

### Claim 9 (depends on 7)

The manufacturing method as claimed in claim 7, wherein the first insulating layer and the second insulating layer are both made of silicon nitride and/or silicon dioxide.