# US 10,120,247 B2 · Manufacturing method for TFT substrate and TFT substrate manufactured by the manufacturing method thereof

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- Number: US 10,120,247 B2
- Document ID: US10120247B2
- Status: Granted
- Kind: B2
- Application number: 15/125,191
- Filed: 2016-04-21
- Published: 2018-05-31
- Granted: 2018-11-06
- Earliest claimed: 2016-03-30
- Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Applicants: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Inventors: Shimin Ge
- Web page: https://patentgrep.com/patent/US10120247B2

## CPC

- G02F 1/13439: {characterised by their electrical, optical, physical properties; materials therefor; method of making}
- G02F 1/136: Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit (G02F1/135 takes precedence)
- G02F 1/136209: {Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element}
- G02F 1/136286: {Wiring, e.g. gate line, drain line}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- H10D 30/6723: {having light shields}
- H10D 30/6756: {Amorphous oxide semiconductors}
- H10D 84/01: Manufacture or treatment
- H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D 86/01: Manufacture or treatment
- H10D 86/021: {of multiple TFTs}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10P 30/202: {characterised by the semiconductor materials}
- H10P 30/21: {of electrically active species}
- H10P 30/22: using masks
- G02F 1/134363: {for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]}
- G02F 1/134372: {for fringe field switching [FFS] where the common electrode is not patterned}
- G02F 1/136236: {using a grey or half tone lithographic process}
- G02F 1/136295: {Materials; Compositions; Manufacture processes}
- G02F 1/13685: {Top gates}
- G02F 2202/10: semiconductor
- H10K 59/123: Connection of the pixel electrodes to the thin film transistors [TFT]
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

The invention provides an array substrate and a manufacturing method thereof. The array substrate comprises a substrate body, a common electrode, a light shield layer, an insulating layer, a polycrystalline silicon layer, a gate insulating layer, a gate electrode, a medium layer and a source-drain electrode. The array substrate is characterized in that the common electrode is formed on the substrate body, the light shield layer is positioned on the common electrode, the insulating layer is positioned on the light shield layer and the common electrode, and the gate electrode is connected with the common electrode through a through hole. The manufacturing method of the array substrate includes the steps: forming the patterned common electrode and the patterned light shield layer by one-time photomask and multiple etching after a transparent conducting layer and a first metal layer are formed on the substrate body, and saving one photomask; forming an electrode through hole communicated with the common electrode and the gate electrode after photomask and etching, and subsequently manufacturing the medium layer and the source-drain electrode. The whole process has seven photomasks, machining process steps of an array substrate tube are simplified, and the manufacturing cost of the array substrate is reduced.

## Claims

### Claim 1

A manufacturing method for thin film transistor (TFT) substrate, which comprises:
Step 1: providing a substrate, and then sequentially depositing a transparent conductive film and a light-shielding film on the substrate;
Step 2: using a semi-permeable mask on the transparent conductive film and the light-shielding film for patterning process to obtain a transparent conductive layer and a common electrode spaced apart on the substrate, and a light-shielding layer over the transparent conductive layer with equal width and aligned at two ends;
Step 3: depositing a buffer layer on the light-shielding layer, the common electrode, and the substrate, and then sequentially depositing an oxide semiconductor layer, an insulating layer, and a gate metal layer on the buffer layer;
Step 4: using a mask on the gate metal layer and the insulating layer for patterning process to obtain a gate and a gate insulating layer with the same width and aligned at two ends;
using the gate and the gate insulating layer as a shielding layer to perform ion doping on the oxide semiconductor layer to convert the region of the oxide semiconductor layer not covered by the gate and the gate insulating layer into oxide conductor;
Step 5: using a mask on the oxide semiconductor layer for patterning process to form an active layer and a pixel electrode connected to the active layer;
the active layer comprising a channel region underneath the gate, a drain contact region located at one side of the channel region, a connection area located at the other side of the channel region and connected to the pixel electrode; wherein the channel region of the active layer being made of an oxide semiconductor material, the drain contact region and the connection region of the active layer, and the pixel electrode being made of an oxide conductor;
Step 6: depositing a first passivation layer on the gate, the active layer and the buffer layer, using a mask on the first passivation layer for patterning process to form a via on the first passivation layer corresponding to the drain contact region; and
Step 7: depositing a drain metal layer on the first passivation layer, using a mask on the drain metal layer for patterning process to obtain a drain, the drain contacting the drain contact region of the active layer through the via, depositing a second passivation layer on the drain and the first passivation layer to form a TFT substrate.

### Claim 2 (depends on 1)

The manufacturing method for TFT substrate as claimed in claim 1, wherein Step 2 further comprises:
Step 21: coating a photoresist layer on the light-shielding film, using a semi-permeable mask on the photoresist layer for patterning process to obtain a first photoresist section and a second photoresist section spaced apart; the first photoresist section having a thickness greater than the thickness of the second photoresist section;
Step 22: using the first photoresist section and the second photoresist section as a stopping layer to perform etching on the transparent conductive film and the light-shielding film to obtain the light-shielding layer and the transparent conductive layer beneath the first photoresist section, and a light-shielding section and the common electrode underneath the second photoresist section;
Step 23: performing an ashing treatment on the first and the second photoresist sections for thinning the first photoresist section and removing the second photoresist section;
Step 24: using the first photoresist section as a stopping layer to perform etching on the light-shielding section to remove the light-shielding section; and
Step 25: removing the remaining first photoresist section.

### Claim 3 (depends on 1)

The manufacturing method for TFT substrate as claimed in claim 1, wherein in Step 2, the semi-permeable mask is a gray tone mask, half tone mask or single slit mask.

### Claim 4 (depends on 1)

The manufacturing method for TFT substrate as claimed in claim 1, wherein in Step 4, the ion doping performed on the oxide semiconductor is through plasma treatment.

### Claim 5 (depends on 1)

The manufacturing method for TFT substrate as claimed in claim 1, wherein in Step 5, the oxide semiconductor is a transparent metal oxide semiconductor material, and the oxide conductor is an ion-doped transparent metal oxide semiconductor material.

### Claim 6

A manufacturing method for thin film transistor (TFT) substrate, which comprises:
Step 1: providing a substrate, and then sequentially depositing a transparent conductive film and a light-shielding film on the substrate;
Step 2: using a semi-permeable mask on the transparent conductive film and the light-shielding film for patterning process to obtain a transparent conductive layer and a common electrode spaced apart on the substrate, and a light-shielding layer over the transparent conductive layer with equal width and aligned at two ends;
Step 3: depositing a buffer layer on the light-shielding layer, the common electrode, and the substrate, and then sequentially depositing an oxide semiconductor layer, an insulating layer, and a gate metal layer on the buffer layer;
Step 4: using a mask on the gate metal layer and the insulating layer for patterning process to obtain a gate and a gate insulating layer with the same width and aligned at two ends;
using the gate and the gate insulating layer as a shielding layer to perform ion doping on the oxide semiconductor layer to convert the region of the oxide semiconductor layer not covered by the gate and the gate insulating layer into oxide conductor;
Step 5: using a mask on the oxide semiconductor layer for patterning process to form an active layer and a pixel electrode connected to the active layer;
the active layer comprising a channel region underneath the gate, a drain contact region located at one side of the channel region, a connection area located at the other side of the channel region and connected to the pixel electrode; wherein the channel region of the active layer being made of an oxide semiconductor material, the drain contact region and the connection region of the active layer, and the pixel electrode being made of an oxide conductor;
Step 6: depositing a first passivation layer on the gate, the active layer and the buffer layer, using a mask on the first passivation layer for patterning process to form a via on the first passivation layer corresponding to the drain contact region; and
Step 7: depositing a drain metal layer on the first passivation layer, using a mask on the drain metal layer for patterning process to obtain a drain, the drain contacting the drain contact region of the active layer through the via, depositing a second passivation layer on the drain and the first passivation layer to form a TFT substrate;
wherein Step 2 further comprising:
Step 21: coating a photoresist layer on the light-shielding film, using a semi-permeable mask on the photoresist layer for patterning process to obtain a first photoresist section and a second photoresist section spaced apart; the first photoresist section having a thickness greater than the thickness of the second photoresist section;
Step 22: using the first photoresist section and the second photoresist section as a stopping layer to perform etching on the transparent conductive film and the light-shielding film to obtain the light-shielding layer and the transparent conductive layer beneath the first photoresist section, and a light-shielding section and the common electrode underneath the second photoresist section;
Step 23: performing an ashing treatment on the first and the second photoresist sections for thinning the first photoresist section and removing the second photoresist section;
Step 24: using the first photoresist section as a stopping layer to perform etching on the light-shielding section to remove the light-shielding section; and
Step 25: removing the remaining first photoresist section;
wherein in Step 2, the semi-permeable mask being a gray tone mask, half tone mask or single slit mask.

### Claim 7 (depends on 6)

The manufacturing method for TFT substrate as claimed in claim 6, wherein in Step 4, the ion doping performed on the oxide semiconductor is through plasma treatment.

### Claim 8 (depends on 6)

The manufacturing method for TFT substrate as claimed in claim 6, wherein in Step 5, the oxide semiconductor is a transparent metal oxide semiconductor material, and the oxide conductor is an ion-doped transparent metal oxide semiconductor material.