# US 10,120,150 B2 · Optical transceiver by FOWLP and DOP multichip integration

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- Number: US 10,120,150 B2
- Document ID: US10120150B2
- Status: Granted
- Kind: B2
- Application number: 15/985,584
- Filed: 2018-05-21
- Published: 2018-09-27
- Granted: 2018-11-06
- Earliest claimed: 2016-03-04
- Assignees: Inphi Corporation
- Applicants: Inphi Corporation
- Inventors: Liang Ding; Radhakrishnan L. Nagarajan; Roberto Coccioli
- Web page: https://patentgrep.com/patent/US10120150B2

## CPC

- G02B 6/428: {containing printed circuit boards [PCB]}
- G02B 6/13: Integrated optical circuits characterised by the manufacturing method
- G02B 6/30: for use between fibre and thin-film device
- G02B 6/4232: {using the surface tension of fluid solder to align the elements, e.g. solder bump techniques (flip-chip mounting techniques in assembly of semiconductor devices H10W72/072)}
- G02B 6/424: {Mounting of the optical light guide}
- G02B 6/4245: {Mounting of the opto-electronic elements}
- G02B 6/4283: {with electrical insulation means}
- G02B 6/4295: {coupling with semiconductor devices activated by light through the light guide, e.g. thyristors, phototransistors}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/00: Interconnections or connectors in packages
- H10W 74/016: {using moulds}
- H10W 90/00: Package configurations
- H10W 90/293: {characterised by non-galvanic coupling between the chips, e.g. capacitive coupling}
- G02B 2006/12121: {Laser}
- G02B 2006/12142: {Modulator}
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- G02B: OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An optical transceiver by hybrid multichip integration. The optical transceiver includes a PCB with a plurality of prefabricated surface bonding sites. A first chip includes a FOWLP package of multiple electronics devices embedded in a dielectric molding layer overlying a dielectric redistribution layer is disposed on the PCB by respectively bonding a plurality of conductor balls between the dielectric redistribution layer and the plurality of prefabricated surface bonding sites while exposing soldering material filled in multiple through-mold vias (TMVs) in the dielectric molding layer. The optical transceiver further includes a second chip configured as a Sipho die comprising photonics devices embedded in a SOI wafer substantially free from any electronics device process. The second chip is stacked over the first chip with multiple conductor bumps being bonded respectively to the soldering material in the multiple TMVs.

## Claims

### Claim 1

An optical system comprising:
an optical transceiver device comprising:
a board with a plurality of prefabricated surface bonding sites;
a first chip comprising multiple electronics devices embedded in a dielectric molding layer overlying a dielectric redistribution layer, the first chip being disposed on the board by bonding the dielectric redistribution layer via a plurality of conductor balls respectively on the plurality of prefabricated surface bonding sites while exposing soldering material filled in multiple through-mold vias (TMVs) formed in the dielectric molding layer and one or more prefabricated recessed structures;
a second chip comprising photonics devices embedded in a silicon on insulator (SOI) wafer having a front surface with multiple conductor bumps and a fiber coupling structure, the second chip being stacked over the first chip with the multiple conductor bumps on the front surface being bonded respectively to the soldering material in the multiple TMVs; and
an optical fiber fixed within V-grooves defined between recessed regions in the front surface of the second chip and the one or more prefabricated recessed structures in the first chip aligned with the fiber coupling structure in the front surface of the second chip, such that a first fiber coupling structure is direct physical contact with a first conductor bump within a first V-groove; and
an interface coupled to the optical transceiver device.

### Claim 2 (depends on 1)

The optical system of claim 1 wherein the first chip comprises multiple electronics dies packaged together using an Embedding Insulation Sheet (EBIS) type material for the dielectric molding layer under a fan-out wafer level package (FOWLP) architecture overlying a HD-8940 Polybenzoxazole (PBO) film for the dielectric redistribution layer.

### Claim 3 (depends on 1)

The optical system of claim 1 wherein the multiple electronics devices comprise a PAM4 application-specific integrated circuit (ASIC) module, a driver module, a trans-impedance amplifier module, and multiple alternating current (AC) coupling capacitors.

### Claim 4 (depends on 1)

The optical system of claim 1 wherein each of the plurality of conductor balls is bonded to a first conductive pad embedded in the dielectric redistribution layer.

### Claim 5 (depends on 4)

The optical system of claim 4 wherein the soldering material filled in each of the multiple TMVs is bonded to a second conductive pad embedded in the dielectric redistribution layer.

### Claim 6 (depends on 1)

The optical system of claim 1 wherein the second chip is a Si-photonics chip.

### Claim 7 (depends on 6)

The optical system of claim 6 wherein the Si-photonics chip comprises Si-based optical waveguides aligned to the one or more fiber coupling structures, a modulator, and multiple photo diodes.

### Claim 8 (depends on 7)

The optical system of claim 7 wherein the dielectric redistribution layer further comprises embedded conductive wires for selectively connecting the multiple electronics devices to at least the modulator and the multiple photo diodes respectively through the soldering material filled in the multiple TMVs and the multiple conductor bumps on the front surface of the second chip.

### Claim 9 (depends on 8)

The optical system of claim 8 further comprising one or more optical fibers being installed in the one or more fiber coupling structures between the front surface of the second chip and the dielectric molding layer of the first chip to couple with corresponding Si-based optical waveguides.

### Claim 10 (depends on 6)

The optical system of claim 6 wherein the second chip further comprises one or more laser diodes mounted on a recessed region of the front surface and electrically coupled via a mounting pad with at one or more of multiple conductor bumps through one or more conductive pads in the dielectric redistribution layer and one or more of the plurality of conductor balls to connect to the board without any external wire bonds.