# US 10,120,028 B2 · Efficient scan latch systems and methods

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- Number: US 10,120,028 B2
- Document ID: US10120028B2
- Status: Granted
- Kind: B2
- Application number: 15/257,781
- Filed: 2016-09-06
- Published: 2017-08-17
- Granted: 2018-11-06
- Earliest claimed: 2012-10-29
- Assignees: NVIDIA Corporation
- Applicants: NVIDIA Corporation
- Inventors: Ilyas Elkin; Ge Yang
- Web page: https://patentgrep.com/patent/US10120028B2

## CPC

- G01R 31/318541: {Scan latches or cell details}
- G01R 31/28: Testing of electronic circuits, e.g. by signal tracer ({EMC, EMP or similar testing of electronic circuits G01R31/002;} testing for short-circuits, discontinuities, leakage or incorrect line connection G01R31/50; checking computers {or computer components} G06F11/00; checking static stores for correct operation G11C29/00 {; testing receivers or transmitters of transmission systems H04B17/00})
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/318536: {Scan chain arrangements, e.g. connections, test bus, analog signals}
- G01R 31/318544: {Scanning methods, algorithms and patterns (G01R31/3183 takes precedence)}
- G01R 31/318555: {Control logic}
- G01R 31/318533: {using scanning techniques, e.g. LSSD, Boundary Scan, JTAG}
- G01R 31/318572: {Input/Output interfaces}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component.

## Claims

### Claim 1

A scan flip flop comprising:
a master latch that passes data input without a scan input associated delay, wherein the master latch is operable to select between a scan in value and a recirculation logical value in a recirculation path;
a slave latch operable to hold a value forwarded from the master latch, wherein the slave latch is also operable to select between a data value and a resulting value forwarded from the master latch, wherein the data value is independent of the scan in value, and outputs of the slave latch are forwarded as the recirculation logical value that is received at the master latch; and
a control component that controls an indication of the selection by the master latch and the slave latch.

### Claim 2 (depends on 1)

The scan flip flop of claim 1, wherein the master latch introduces a delay to a scan input value before passing it on to the slave latch.

### Claim 3 (depends on 1)

The scan flip flop of claim 1, wherein a data input is not subjected to a parasitic load associated with a selection between a scan input and a recirculation.

### Claim 4 (depends on 1)

The scan flip flop of claim 1, wherein the choice of a data input avoids a parasitic load associated with a selection between a recirculation and a data input.

### Claim 5 (depends on 1)

The scan flip flop of claim 1, wherein the master latch is at least partially controlled with a gated clock signal.

### Claim 6 (depends on 1)

The scan flip flop of claim 1, wherein the slave latch is operable to pass input data without a delay associated with the master latch.

### Claim 7 (depends on 1)

The scan flip flop of claim 1, wherein the master latch and slave latch are operable to introduce a delay to scan input.

### Claim 8 (depends on 1)

The scan flip flop of claim 1, wherein the master latch is configured in the recirculation path of the slave latch.

### Claim 9

A method comprising:
receiving a scan enable indication at a master latch;
selecting between a scan input and a recirculation value in the master latch;
choosing between a corresponding data input and results of the selecting, wherein the choosing is performed in a slave latch and the choosing is performed after the selecting in the master latch, wherein data input is independent of the scan input and results of a slave latch choice are forwarded as the recirculation logical value of the scan input;
and
choosing between the corresponding data input and the results of the selecting.

### Claim 10 (depends on 9)

The method of claim 9, wherein data input is forwarded directly to the slave latch without another component delay when a choice is the data input.

### Claim 11 (depends on 9)

The method of claim 9, wherein scan input is delayed by the master latch before forwarding to the slave latch when a choice is the scan input.

### Claim 12 (depends on 9)

The method of claim 9, wherein the selecting is performed in a recirculation path.

### Claim 13 (depends on 9)

The method of claim 9, wherein the choice of a data input is not subjected to a parasitic load associated with a selection between a scan input and a recirculation.

### Claim 14 (depends on 9)

The method of claim 9, further comprising controlling said selecting with a gated clock signal.

### Claim 15

A scan flip flop comprising:
a master latch-operable to select between a scan in value and a recirculation logical value;
a slave latch operable to select between a data value and a resulting value forwarded from the master latch, wherein the data value is independent of the scan in value, and outputs of the slave latch are forwarded as the recirculation logical value that is received at the master latch; and
a control component that controls an indication of the selection by the master latch and the slave latch.

### Claim 16 (depends on 15)

A scan flip flop of claim 15, wherein the a slave latch is operable to hold a value forwarded from the master latch.

### Claim 17 (depends on 15)

A scan flip flop of claim 15, wherein the master latch is at least partially controlled with a gated clock signal.

### Claim 18 (depends on 15)

A scan flip flop of claim 15, wherein the slave latch is operable to forward a value while avoiding a delay associated with the master latch.