# US 10,120,025 B2 · Functional core circuitry with serial scan test expected, mask circuitry

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- Number: US 10,120,025 B2
- Document ID: US10120025B2
- Status: Granted
- Kind: B2
- Application number: 15/795,943
- Filed: 2017-10-27
- Published: 2018-02-22
- Granted: 2018-11-06
- Earliest claimed: 2001-11-28
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Lee D. Whetsel; Alan Hales
- Web page: https://patentgrep.com/patent/US10120025B2

## CPC

- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 1/07342: {the body of the probe being at an angle other than perpendicular to test object, e.g. probe card}
- G01R 31/318536: {Scan chain arrangements, e.g. connections, test bus, analog signals}
- G01R 31/318541: {Scan latches or cell details}
- G01R 31/318544: {Scanning methods, algorithms and patterns (G01R31/3183 takes precedence)}
- G01R 31/318547: {Data generators or compressors}
- G01R 31/318555: {Control logic}
- G01R 31/318558: {Addressing or selecting of subparts of the device under test}
- G01R 31/318563: {Multiple simultaneous testing of subparts}
- G01R 31/318566: {Comparators; Diagnosing the device under test}
- G01R 31/318572: {Input/Output interfaces}
- G01R 31/31924: {Voltage or current aspects, e.g. driver, receiver}
- G01R 31/31926: {Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

## Claims

### Claim 1

An integrated circuit die comprising:
(a) die input and output pads including a first die input pad and a second die input pad;
(b) a core of functional circuitry having inputs and outputs coupled to the die input and output pads, the core circuitry including:
i. a first core input coupled to the first die input pad, a first core output, a second core input coupled to the second die input pad, and a second core output;
ii. a first scan path having a first scan path input coupled to the first core input and a first scan path output coupled to the first core output;
iii. a second scan path having a second scan path input coupled to the second core input and a second scan path output coupled to the second core output; and
(c) a first test circuit having a first core input coupled to the first core output, a first expected data input coupled to a third die pad, a first mask data input coupled to a fourth die pad, a first scan path input, and a first scan path output;
(d) a second test circuit having a second core input coupled to the second core output, a second expected data input coupled to a fifth die pad, a second mask data input coupled to a sixth die pad, a second scan path input, and a second scan path output; and
(e) a die serial scan path having an input coupled to a die input pad, an output coupled to a die output pad, and being connected in series with the first scan path input, the first scan path output, the second scan path input, and the second scan path output.

### Claim 2 (depends on 1)

The integrated circuit die of claim 1 in which the die includes a first buffer coupling the first die input pad to the first core input, and a second buffer coupling the second die input pad to the second core input.

### Claim 3 (depends on 1)

The integrated circuit die of claim 1 in which the first expected data input and second expected data input are separate from one another.

### Claim 4 (depends on 1)

The integrated circuit die of claim 1 in which the first mask data input and second mask data input are separate from one another.

### Claim 5 (depends on 1)

The integrated circuit die of claim 1 in which the die includes a first buffer coupling the input of the die serial scan path to a die input pad.

### Claim 6 (depends on 1)

The integrated circuit die of claim 1 in which the first scan path, the second scan path, and the die serial scan path are separate from one another.