# US 10,120,024 B2 · Multi-stage test response compactors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,120,024 B2 - Document ID: US10120024B2 - Status: Granted - Kind: B2 - Application number: 15/723,112 - Filed: 2017-10-02 - Published: 2018-06-07 - Granted: 2018-11-06 - Earliest claimed: 2006-02-17 - Assignees: Mentor Graphics Corporation - Applicants: Mentor Graphics Corporation - Inventors: Janusz Rajski; Jerzy Tyszer; Grzegorz Mrugalski; Mark Kassab; Wu-Tung Cheng - Web page: https://patentgrep.com/patent/US10120024B2 ## CPC - G01R 31/3177: Testing of logic operation, e.g. by logic analysers - G01R 31/2851: {Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801)} - G01R 31/31723: {Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926)} - G01R 31/31727: {Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922)} - G01R 31/318547: {Data generators or compressors} - G01R 31/318563: {Multiple simultaneous testing of subparts} - G01R 31/318566: {Comparators; Diagnosing the device under test} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits. ## Claims ### Claim 1 An apparatus for compacting test responses of a circuit-under-test, the apparatus comprising: a first compactor comprising a plurality of first-compactor inputs and a first-compactor output; a register comprising a register input and a plurality of register outputs, the register input being coupled to the first-compactor output, the register being operable to load test response bits through the register input and to output the test response bits in parallel through the plurality of register outputs; a second compactor comprising a plurality of second-compactor inputs and a second-compactor output, the plurality of second-compactor inputs being coupled to the plurality of register outputs, the second compactor being a spatial compactor; a first set of masking logic coupled to the plurality of first-compactor inputs; a second set of masking logic coupled between the plurality of register outputs and the plurality of second-compactor inputs; and selection logic having one or more selection-logic inputs and a plurality of selection-logic outputs, the plurality of selection-logic outputs being coupled to respective inputs of the first set of masking logic and respective inputs of the second set of masking logic, the selection logic being operable to selectively control the first set of masking logic and the second set of masking logic in response to one or more masking instruction bits received at the one or more selection-logic inputs. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the second spatial compactor is feedback free. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the second spatial compactor comprises a network of XOR or XNOR gates. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the second spatial compactor is a pipelined spatial compactor. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the register comprises two or more sequential elements coupled in series. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the register is operable to serially load the test response bits. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the first compactor comprises a plurality of first-compactor outputs. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the second compactor comprises a plurality of second-compactor outputs. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the selection logic comprises a network of logic gates configured according to polynomials. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein at least some of the logic gates are XOR or XNOR gates. ### Claim 11 (depends on 9) The apparatus of claim 9, wherein the polynomials describe respective relationships between at least one selection logic input and at least one selection logic output. ### Claim 12 (depends on 1) The apparatus of claim 1, wherein the register is a first register, wherein the selection logic comprises a plurality of selection-logic inputs, and wherein the apparatus further comprises a second register having a second-register input and a plurality of second-register outputs, the plurality of second-register outputs being coupled to the plurality of selection-logic inputs. ### Claim 13 (depends on 1) The apparatus of claim 1, wherein the masking instruction bits are uncompressed bits received from an external tester, an on-chip memory, or an on-chip decompressor. ### Claim 14 One or more non-transitory computer-readable media storing circuit design information for implementing an apparatus comprising: a first compactor comprising a plurality of first-compactor inputs and a first-compactor output; a register comprising a register input and a plurality of register outputs, the register input being coupled to the first-compactor output, the register being operable to load test response bits through the register input and to output the test response bits in parallel through the plurality of register outputs; a second compactor comprising a plurality of second-compactor inputs and a second-compactor output, the plurality of second-compactor inputs being coupled to the plurality of register outputs, the second compactor being a spatial compactor; a first set of masking logic coupled to the plurality of first-compactor inputs; a second set of masking logic coupled between the plurality of register outputs and the plurality of second-compactor inputs; and selection logic having one or more selection-logic inputs and a plurality of selection-logic outputs, the plurality of selection-logic outputs being coupled to respective inputs of the first set of masking logic and respective inputs of the second set of masking logic, the selection logic being operable to selectively control the first set of masking logic and the second set of masking logic in response to one or more masking instruction bits received at the one or more selection-logic inputs. ### Claim 15 One or more non-transitory computer-readable media storing computer-executable instructions for causing a computer to create an apparatus comprising: a first compactor comprising a plurality of first-compactor inputs and a first-compactor output; a register comprising a register input and a plurality of register outputs, the register input being coupled to the first-compactor output, the register being operable to load test response bits through the register input and to output the test response bits in parallel through the plurality of register outputs; a second compactor comprising a plurality of second-compactor inputs and a second-compactor output, the plurality of second-compactor inputs being coupled to the plurality of register outputs, the second compactor being a spatial compactor; a first set of masking logic coupled to the plurality of first-compactor inputs; a second set of masking logic coupled between the plurality of register outputs and the plurality of second-compactor inputs; and selection logic having one or more selection-logic inputs and a plurality of selection-logic outputs, the plurality of selection-logic outputs being coupled to respective inputs of the first set of masking logic and respective inputs of the second set of masking logic, the selection logic being operable to selectively control the first set of masking logic and the second set of masking logic in response to one or more masking instruction bits received at the one or more selection-logic inputs. ### Claim 16 (depends on 14) The one or more non-transitory computer-readable media of claim 14, wherein the register comprises two or more sequential elements coupled in series. ### Claim 17 (depends on 14) The one or more non-transitory computer-readable media of claim 14, wherein the register is operable to serially load the test response bits. ### Claim 18 (depends on 15) The one or more non-transitory computer-readable media of claim 15, wherein the register comprises two or more sequential elements coupled in series. ### Claim 19 (depends on 15) The one or more non-transitory computer-readable media of claim 15, wherein the register is operable to serially load the test response bits.