# US 10,120,023 B2 · 3D tap and scan port architectures

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- Number: US 10,120,023 B2
- Document ID: US10120023B2
- Status: Granted
- Kind: B2
- Application number: 15/991,581
- Filed: 2018-05-29
- Published: 2018-09-27
- Granted: 2018-11-06
- Earliest claimed: 2012-09-19
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Lee D. Whetsel
- Web page: https://patentgrep.com/patent/US10120023B2

## CPC

- G01R 31/31723: {Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926)}
- G01R 31/2896: {Testing of IC packages; Test features related to IC packages (containers per se H10W76/10, encapsulations per se H10W74/00)}
- G01R 31/31724: {Test controller, e.g. BIST state machine (for scan test G01R31/318555)}
- G01R 31/31727: {Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922)}
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/3183: Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R 31/318513: {Test of Multi-Chip-Moduls}
- G01R 31/318552: {Clock circuits details}
- G01R 31/318555: {Control logic}
- G01R 31/318558: {Addressing or selecting of subparts of the device under test}
- G01R 31/318572: {Input/Output interfaces}
- G01R 31/318594: {Timing aspects (clock circuits G01R31/318552)}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

## Claims

### Claim 1

An integrated circuit die comprising:
(a) a first side including a test clock in signal contact point, a test mode select in signal contact point, a test reset in signal contact point, a test data in signal contact point, a test data out signal contact point, and an UP in signal contact point;
(b) a CSU unit having an input coupled with the test clock in signal contact point, an input coupled to a test mode select in signal contact point, a capture shift output, an update output, and a scan clock output;
(c) gating circuitry having an input coupled with the capture shift output, an input coupled with the update output, an input coupled with the scan clock output, an input coupled with the UP in signal contact point, a gated capture shift output, a gated update output, and a gated scan clock output; and
(d) a test data register having an input coupled with the gated capture shift output, an input coupled with the gated update output, an input coupled with the gated scan clock output, an input coupled with the test reset in signal contact point, an input coupled with the test data in signal contact point, and an output coupled with the test data out signal contact point.

### Claim 2 (depends on 1)

The integrated circuit die of claim 1 in which the test data register is a serial register circuit.

### Claim 3 (depends on 1)

The integrated circuit die of claim 1 in which the test data register is an embedded instrument circuit.

### Claim 4 (depends on 1)

The integrated circuit die of claim 1 in which the test data register is a scan compression circuit.

### Claim 5 (depends on 1)

The integrated circuit die of claim 1 in which the test data register is a debug circuit.

### Claim 6 (depends on 1)

The integrated circuit die of claim 1 in which the test data register is a trace circuit.

### Claim 7 (depends on 1)

The integrated circuit die of claim 1 in which the test data register is a diagnostic circuit.

### Claim 8 (depends on 1)

The integrated circuit die of claim 1 in which the test data register is a tuning circuit.

### Claim 9 (depends on 1)

The integrated circuit die of claim 1 in which the test data register is a boundary scan circuit.

### Claim 10 (depends on 1)

The integrated circuit die of claim 1 in which the test data register is a built in test circuit.

### Claim 11 (depends on 1)

The integrated circuit die of claim 1 in which the test data register is a programming circuit.

### Claim 12 (depends on 1)

The integrated circuit die of claim 1 in which the test data register is a memory repair circuit.

### Claim 13 (depends on 1)

The integrated circuit die of claim 1 in which the first side is a bottom side.