# US 10,120,022 B2 · Tap flip flop, gate, and compare circuitry on rising SCK

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- Number: US 10,120,022 B2
- Document ID: US10120022B2
- Status: Granted
- Kind: B2
- Application number: 15/467,517
- Filed: 2017-03-23
- Published: 2017-07-06
- Granted: 2018-11-06
- Earliest claimed: 2008-04-02
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Lee D. Whetsel
- Web page: https://patentgrep.com/patent/US10120022B2

## CPC

- G01R 31/31723: {Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926)}
- G01R 31/31725: {Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937)}
- G01R 31/31727: {Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922)}
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/318552: {Clock circuits details}
- G01R 31/318566: {Comparators; Diagnosing the device under test}
- G01R 31/318594: {Timing aspects (clock circuits G01R31/318552)}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test.

## Claims

### Claim 1

A device comprising:
A. a scan data input;
B. a test clock input;
C. a test mode select input;
D. test access port circuitry having an input coupled to the test clock input, an input coupled to the test mode select input, a scan clock output, and a control output;
E. a scan register having an input coupled to the scan data input, an input coupled to the scan clock output, a gated scan enable input, and a scan output;
F. an inverter having an input coupled to the test clock input and an inverted test clock output;
G. a flip flop having an input coupled to the test mode select input, an input coupled to the inverted test clock output, and a data output;
H. gate circuitry having an input coupled to the data output of the flip flop, an input coupled to the control output, and a gated scan enable output coupled to the gated scan enable input; and
I. compare circuitry having a first input coupled to the scan output of the scan register.

### Claim 2 (depends on 1)

The device of claim 1 including combinational logic having parallel stimulus inputs and parallel response outputs and in which the scan register includes parallel stimulus outputs coupled to the parallel stimulus inputs and parallel response inputs coupled to the parallel response outputs.

### Claim 3 (depends on 1)

The device of claim 1 in which the compare circuitry includes an input coupled to the scan clock output and an input coupled to the gated scan enable output.

### Claim 4 (depends on 1)

The device of claim 1 in which the compare circuitry includes a serial test data input and a serial test data output separate from the scan data input and the first input.

### Claim 5 (depends on 1)

The device of claim 1 in which the test access port circuitry includes a state machine operating in a Test Logic Reset state, a Run Test/Idle state, Capture states, Shift states, Exit1 states, Pause states, Exit2 states, and Update states.

### Claim 6 (depends on 1)

The device of claim 1 in which the gate circuitry is an AND gate.

### Claim 7

An integrated circuit scan test architecture comprising:
A. combinational logic having parallel stimulus inputs and parallel response outputs;
B. a scan data input, a test clock input, and a test mode select input;
C. test access port circuitry having a state machine operating in states, an input coupled to the test clock input, an input coupled to the test mode select input, a scan clock output, and a control output;
D. a scan register having an input coupled to the scan data input, an input coupled to the scan clock output, parallel stimulus outputs coupled to the parallel stimulus inputs, parallel response inputs coupled to the parallel response outputs, a gated scan enable input, and a scan output;
E. an inverter having an input coupled to the test clock input and an inverted test clock output;
F. a flip flop having an input coupled to the test mode select input, an input coupled to the inverted test clock output, and a data output;
G. gate circuitry having an input coupled to the data output of the flip flop, an input coupled to the control output, and a gated scan enable output coupled to the gated scan enable input; and
H. compare circuitry having a first input coupled to the scan output of the scan register.

### Claim 8 (depends on 7)

The architecture of claim 7 in which the compare circuitry includes an input coupled to the scan clock output and an input coupled to the gated scan enable output.

### Claim 9 (depends on 7)

The architecture of claim 7 in which the compare circuitry includes a serial test data input and a serial test data output separate from the scan data input and the first input.

### Claim 10 (depends on 7)

The architecture of claim 7 in which the state machine operates in the states of a Test Logic Reset state, a Run Test/Idle state, Capture states, Shift states, Exit1 states, Pause states, Exit2 states, and Update states.

### Claim 11 (depends on 7)

The architecture of claim 7 in which the gate circuitry is an AND gate.