# US 10,120,019 B2 · Automated method for analyzing a board having a plurality of FPGA components > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,120,019 B2 - Document ID: US10120019B2 - Status: Granted - Kind: B2 - Application number: 14/907,501 - Filed: 2014-07-08 - Published: 2016-06-09 - Granted: 2018-11-06 - Earliest claimed: 2013-07-26 - Assignees: Mentor Graphics Corporation - Applicants: Mentor Graphics Corporation - Inventors: Matthieu Tuna; Zied Marrakchi; Christophe Alexandre - Web page: https://patentgrep.com/patent/US10120019B2 ## CPC - G01R 31/2882: {Testing timing characteristics} - G01R 31/2834: {Automated test systems [ATE]; using microprocessors or computers (G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736)} - G01R 31/31725: {Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937)} - G06F 30/331: with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation - G06F 30/3312: Timing analysis - G06F 30/3315: using static timing analysis [STA] - G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] - G06F 30/347: Physical level, e.g. placement or routing - G06F 30/333: Design for testability [DFT], e.g. scan chain or built-in self-test [BIST] - G06F 2119/12: Timing analysis or timing optimisation - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract The disclosed technology relates to analyzing an electronic board having a plurality of FPGAs that are interconnected and programmed to implement a logic design. One example method comprises: setting up a graph representing the board; determining, for each FPGA, by means of an FPGA-specific static temporal analysis tool, the time for travelling over each path portion that passes through said FPGA, each travel time corresponding to the sum of the times for carrying out the logical operations applied to the signal in the FPGA; determining the inter-FPGA time for travelling over each inter-FPGA portion represented by a link in the graph; and determining the time for travelling over each path of the board by summing the intra-FPGA travel times and the inter-FPGA travel times associated with each link of the graph. ## Claims ### Claim 1 An automated method for developing a multi-FPGA prototype of an application-specific integrated circuit (ASIC), wherein the multi-FPGA prototype is implemented on an electronic board having a plurality of FPGA-type programmable chips (FPGAs) including a first FPGA and a second FPGA, the method comprising: segmenting a netlist of the ASIC according to a number of the plurality FPGAs; constructing a synchronization graph having a plurality of edges which correspond to communication paths of the netlist from respective originating sequential cells to respective destination sequential cells; in at least one case where a subset of the communication paths being communicated between the first and second FPGAs exceeds a number of physical connections between the first and second FPGAs on the electronic board: determining travel times of each of the subset of the communication paths for respective signals by combining: a first intra-FPGA travel time corresponding to time required to perform one or more logical operations within the first FPGA on the respective signal; an inter-FPGA travel time for an inter-chip portion of the each communication path between the first FPGA to the second FPGA; and a second intra-FPGA travel time corresponding to time required to perform one or more logical operations within the second FPGA on the respective signal; integrating one or more serializers and one or more deserializers into the first and second FPGAs to multiplex selected ones of the subset of communication paths, wherein one or more of the selected communication paths have lower travel time and higher degree of multiplexing than one or more non-selected communication paths of the subset of communication paths; and configuring the electronic board to implement the ASIC netlist and the integrated serializer(s) and deserializer(s). ### Claim 2 (depends on 1) The automated method of claim 1, wherein the first and second intra-FPGA travel times are based on a standard delay value per logic cell traversed by the each communication path within the first and second FPGAs respectively. ### Claim 3 (depends on 1) The automated method of claim 1, further comprising, subsequent to the integrating and prior to the configuring, performing static timing analysis of the netlist of the ASIC and the integrated serializer(s) and deserializer(s). ### Claim 4 (depends on 3) The automated method of claim 3, wherein delays determined from the static timing analysis are integrated into the synchronization graph. ### Claim 5 (depends on 1) The automated method of claim 1, further comprising repeating the travel time determination for a multiplexed communication path incorporating a first serializer of the integrated serializers and a first deserializer of the integrated deserializer, wherein the first serializer and the first deserializer are treated as combinational components. ### Claim 6 (depends on 5) The automated method of claim 5, wherein the multiplexed communication path is part of a group of communication paths sharing the first serializer and, for the repeated travel time determination, the inter-FPGA travel time further includes a first delay at the first serializer which is dependent on a processing rank of the multiplexed communication path among the group of communication paths. ### Claim 7 (depends on 5) The automated method of claim 5, wherein the multiplexed communication path is part of a group of communication paths sharing the first deserializer and, for the repeated travel time determination, the inter-FPGA travel time further includes a second delay at the first deserializer which is dependent on a processing rank of the multiplexed communication path among the group of communication paths. ### Claim 8 (depends on 5) The automated method of claim 5, wherein the multiplexed communication path is part of a group of communication paths sharing the first serializer and/or sharing the first deserializer, and further comprising, in at least one case: determining a synchronization violation of the multiplexed communication path; and changing a processing rank of the multiplexed communication path among the group of communication paths. ### Claim 9 (depends on 8) The automated method of claim 8, wherein determining the synchronization violation comprises determining that the respective signal on the multiplexed communication path arrives too late at the second FPGA over the multiplexed communication path, and wherein the processing rank is advanced to be processed earlier. ### Claim 10 (depends on 8) The automated method of claim 8, wherein determining the synchronization violation comprises determining that the respective signal on the multiplexed communication path arrives too early at the second FPGA over the multiplexed communication path, and wherein the processing rank is delayed to be processed later. ### Claim 11 (depends on 8) The automated method of claim 8, further comprising verifying that the changing of processing rank results in clearing of the synchronization violation. ### Claim 12 (depends on 5) The automated method of claim 5, wherein the repeated travel time determination for a multiplexed communication path comprises, for a first signal of the respective signals on the multiplexed communication path: determining a first instant at which the first signal is emitted from the first FPGA; and determining a second instant at which the first signal is delivered to the second FPGA. ### Claim 13 (depends on 1) The automated method of claim 1, wherein the act of combining the first intra-FPGA travel time, the inter-FPGA travel time, and the second intra-FPGA travel time comprises summing the first intra-FPGA travel time, the inter-FPGA travel time, and the second intra-FPGA travel time. ### Claim 14 (depends on 1) The automated method of claim 1, wherein the inter-FPGA travel time is based on a length of the each communication path between the first FPGA and the second FPGA and on a corresponding signal transfer speed. ### Claim 15 (depends on 1) The automated method of claim 1, wherein the integrated serializer(s) and deserializer(s) are incorporated in the synchronization graph. ### Claim 16 (depends on 1) The automated method of claim 1, wherein at least one of the integrated serializers and at least one of the integrated deserializers are driven by a fast clock which has a higher frequency than a base clock of the electronic board. ### Claim 17 (depends on 1) The automated method of claim 1, wherein a portion of content of the first FPGA and a portion of content of the second FPGA are excluded from the synchronization graph. ### Claim 18 A system for developing a multi-FPGA prototype of an application-specific integrated circuit (ASIC), wherein the multi-FPGA prototype is implemented on an electronic board having a plurality of FPGA-type programmable chips (FPGAs) including a first FPGA and a second FPGA, the system comprising: one or more computers configured to: segment a netlist of the ASIC according to a number of the plurality FPGAs; construct a synchronization graph having a plurality of edges which correspond to communication paths of the netlist from respective originating sequential cells to respective destination sequential cells; in at least one case where a subset of the communication paths being communicated between the first and second FPGAs exceeds a number of physical connections between the first and second FPGAs on the electronic board: determine travel times of each of the subset of the communication paths for respective signals by combining: a first intra-FPGA travel time corresponding to time required to perform one or more logical operations within the first FPGA on the respective signal; an inter-FPGA travel time for an inter-chip portion of the each communication path between the first FPGA to the second FPGA; and a second intra-FPGA travel time corresponding to time required to perform one or more logical operations within the second FPGA on the respective signal; integrate one or more serializers and one or more deserializers into the first and second FPGAs to multiplex selected ones of the subset of communication paths, wherein one or more of the selected communication paths have a lower travel time and a higher degree of multiplexing than one or more non-selected communication paths of the subset of communication paths; and configure the electronic board to implement the ASIC netlist and the integrated serializer(s) and deserializer(s). ### Claim 19 (depends on 18) The system of claim 18, wherein the one or more computers are further configured to: repeat the travel time determination for a multiplexed communication path incorporating a first serializer of the integrated serializers and a first deserializer of the integrated deserializer; wherein the first serializer and the first deserializer are treated as combinational components; and wherein the multiplexed communication path is part of a group of communication paths sharing the first serializer and/or sharing the first deserializer; and in at least one case, determine a synchronization violation of the multiplexed communication path. ### Claim 20 (depends on 19) The system of claim 19, wherein the one or more computers are further configured to: change a processing rank of the multiplexed communication path among the group of communication paths; and verify that the changing of processing rank results in clearing of the synchronization violation.