# US 10,119,839 B2 · Sensor circuit and method

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- Number: US 10,119,839 B2
- Document ID: US10119839B2
- Status: Granted
- Kind: B2
- Application number: 15/135,533
- Filed: 2016-04-21
- Published: 2017-01-26
- Granted: 2018-11-06
- Earliest claimed: 2015-04-23
- Assignees: NXP B.V.
- Applicants: NXP B.V.
- Inventors: Rameswor Shrestha; Franciscus Widdershoven
- Web page: https://patentgrep.com/patent/US10119839B2

## CPC

- G01D 5/24: by varying capacitance
- G01R 27/2605: {Measuring capacitance (capacitive sensors G01D5/24)}
- H03K 17/9622: {using a plurality of detectors, e.g. keyboard}
- H03K 2217/960725: Charge-transfer
- H03K 2217/96074: Switched capacitor
- H03K 2217/960745: Capacitive differential; e.g. comparison with reference capacitance
- G01D: MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A sensor circuit and method. The circuit includes a first subcircuit that includes a first sense capacitor, a first integration capacitor, and a first clock input for receiving a first digital clock signal for initiating discharge of the first integration capacitor at time T. The circuit includes a second subcircuit that includes a second sense capacitor, a second integration capacitor, and a second clock input for receiving a second digital clock signal for initiating discharge of the second integration capacitor at time T+Td. A rate of discharge of the first and second integration capacitors is at least partly determined by a capacitance of the first and second sense capacitor, respectively. At time Teval, after initiation of discharge of the first and second sense capacitors, the extent to which the first and second integration capacitors have discharged is compared. A digital signal indicating the result of the comparison is outputted.

## Claims

### Claim 1

A sensor circuit comprising:
a first subcircuit comprising:
a first sense capacitor;
a first integration capacitor, and
a first clock input for receiving a first digital clock signal for initiating discharge of the first integration capacitor at time T, wherein a rate of discharge of the first integration capacitor is at least partly determined by a capacitance of the first sense capacitor;
a second subcircuit comprising:
a second sense capacitor;
a second integration capacitor, and
a second clock input for receiving a second digital clock signal for initiating discharge of the second integration capacitor at time T+Td, wherein a rate of discharge of the second integration capacitor is at least partly determined by a capacitance of the second sense capacitor,
wherein the circuit is operable:
at time Teval, after initiation of discharge of the first and second integration capacitors, to compare the extent to which the first and second integration capacitors have discharged, thereby to compare the capacitance of the first sense capacitor to the capacitance of the second sense capacitor; and
to output a digital signal indicating the result of the comparison,
wherein the sensor circuit further comprises a delay generator for varying Td in a plurality of measurements for comparing the capacitance of the first sense capacitor to the capacitance of the second sense capacitor.

### Claim 2 (depends on 1)

The sensor circuit of claim 1, wherein the first integration capacitor comprises a first decoupling capacitor connected to discharge through a first node of the first subcircuit, wherein the second integration capacitor comprises a second decoupling capacitor connected to discharge through a second node of the second subcircuit, and wherein the sensor circuit further comprises a latch having inputs connected to said nodes, wherein the latch is operable to set or reset according to the voltage at the first node compared to the voltage at the second node.

### Claim 3 (depends on 2)

The sensor circuit of claim 2, wherein the latch comprises a pair of cross-coupled field effect transistors, wherein a first of said transistors has a gate connected to the first node and wherein a second of said transistors has a gate connected to the second node.

### Claim 4 (depends on 1)

The sensor circuit of claim 1, wherein:
the first subcircuit further comprises a first inverter having an input for receiving the first digital clock signal and an output connected to the first sense capacitor, wherein the first integration capacitor is connected to a power supply input of the first inverter; and
the second subcircuit further comprises a second inverter having an input for receiving the second digital clock signal and an output connected to the second sense capacitor, wherein the second integration capacitor is connected to a power supply input of the second inverter.

### Claim 5 (depends on 4)

The sensor circuit of claim 4, wherein the first inverter and the second inverter each include a transmission gate.

### Claim 6 (depends on 1)

The sensor circuit of claim 1, wherein one of said first and second sense capacitors is a reference capacitor for sensing a reference capacitance to be compared to the capacitance of the other of said first and second sense capacitors.

### Claim 7 (depends on 1)

The sensor circuit of claim 1, further comprising logic connected to receive the digital signal indicating the result of said comparison from said output, wherein the logic is operable to:
control the delay generator for varying Td in a plurality of measurements for comparing the capacitance of the first sense capacitor to the capacitance of the second sense capacitor, and
to convert the results of the measurements into a digital word.

### Claim 8 (depends on 7)

The sensor circuit of claim 7, wherein said logic comprises successive approximation logic.

### Claim 9 (depends on 1)

A sensor array comprising a plurality of sensor circuits according to claim 1.

### Claim 10 (depends on 9)

A secure integrated circuit comprising the sensor array of claim 9, wherein the sensor circuits are operable to detect a change in capacitance in their sense capacitors associated with a tampering of the integrated circuit.

### Claim 11

A method for comparing the capacitance of a first sense capacitor to the capacitance of a second sense capacitor of a sensor circuit, the method comprising:
using a first digital clock signal to initiate, at time T, discharge of a first integration capacitor, wherein a rate of discharge of the first integration capacitor is at least partly determined by the capacitance of the first sense capacitor;
using a second digital clock signal to initiate, at time T+Td, discharge of a second integration capacitor, wherein a rate of discharge of the second integration capacitor is at least partly determined by the capacitance of the second sense capacitor;
at time Teval, after initiation of discharge of the first and second integration capacitors, comparing the extent to which the first and second integration capacitors have discharged, thereby to compare the capacitance of the first sense capacitor to the capacitance of the second sense capacitor; and
outputting a digital signal indicating the result of the comparison, wherein the method further comprises performing a plurality of measurements by repeating the steps of:
initiating discharge of the first integration capacitor;
initiating discharge of the second integration capacitor, and
comparing the extent to which the first and second integration capacitors have discharged,
for a plurality of values of Td, to evaluate the capacitance of the first and/or the second capacitor.

### Claim 12 (depends on 11)

The method of claim 11, wherein the outputted digital signal is indicative of which of the first sense capacitor and the second sense capacitor has the largest capacitance.

### Claim 13 (depends on 11)

The method of claim 11, comprising converting the results of the plurality of measurements into a digital word.

### Claim 14

A sensor circuit comprising:
a first subcircuit comprising:
a first sense capacitor;
a first integration capacitor, and
a first clock input for receiving a first digital clock signal for initiating discharge of the first integration capacitor at time T, wherein a rate of discharge of the first integration capacitor is at least partly determined by a capacitance of the first sense capacitor;
a second subcircuit comprising:
a second sense capacitor;
a second integration capacitor, and
a second clock input for receiving a second digital clock signal for initiating discharge of the second integration capacitor at time T+Td, wherein a rate of discharge of the second integration capacitor is at least partly determined by a capacitance of the second sense capacitor,
wherein the circuit is operable:
at time Teval, after initiation of discharge of the first and second integration capacitors, to compare the extent to which the first and second integration capacitors have discharged, thereby to compare the capacitance of the first sense capacitor to the capacitance of the second sense capacitor; and
to output a digital signal indicating the result of the comparison, wherein:
the first subcircuit further comprises a first inverter having an input for receiving the first digital clock signal and an output connected to the first sense capacitor, wherein the first integration capacitor is connected to a power supply input of the first inverter, and
the second subcircuit further comprises a second inverter having an input for receiving the second digital clock signal and an output connected to the second sense capacitor, wherein the second integration capacitor is connected to a power supply input of the second inverter.

### Claim 15 (depends on 14)

The sensor circuit of claim 14, wherein the first integration capacitor comprises a first decoupling capacitor connected to discharge through a first node of the first subcircuit, wherein the second integration capacitor comprises a second decoupling capacitor connected to discharge through a second node of the second subcircuit, and wherein the sensor circuit further comprises a latch having inputs connected to said nodes, wherein the latch is operable to set or reset according to the voltage at the first node compared to the voltage at the second node.

### Claim 16 (depends on 15)

The sensor circuit of claim 15, wherein the latch comprises a pair of cross-coupled field effect transistors, wherein a first of said transistors has a gate connected to the first node and wherein a second of said transistors has a gate connected to the second node.

### Claim 17 (depends on 14)

The sensor circuit of claim 14, wherein the first inverter and the second inverter each include a transmission gate.

### Claim 18 (depends on 14)

The sensor circuit of claim 14, wherein one of said first and second sense capacitors is a reference capacitor for sensing a reference capacitance to be compared to the capacitance of the other of said first and second sense capacitors.

### Claim 19 (depends on 14)

The sensor circuit of claim 14, further comprising a delay generator for varying Td in a plurality of measurements for comparing the capacitance of the first sense capacitor to the capacitance of the second sense capacitor.

### Claim 20 (depends on 19)

The sensor circuit of claim 19, further comprising logic connected to receive the digital signal indicating the result of said comparison from said output, wherein the logic is operable to:
control the delay generator for varying Td in a plurality of measurements for comparing the capacitance of the first sense capacitor to the capacitance of the second sense capacitor, and
to convert the results of the measurements into a digital word.