# US 10,118,816 B2 · Method of forming a protective coating for a packaged semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,118,816 B2 - Document ID: US10118816B2 - Status: Granted - Kind: B2 - Application number: 15/388,557 - Filed: 2016-12-22 - Published: 2017-04-13 - Granted: 2018-11-06 - Earliest claimed: 2015-08-24 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Klaus Elian; Horst Theuss - Web page: https://patentgrep.com/patent/US10118816B2 ## CPC - B81B 7/0038: {using materials for controlling the level of pressure, contaminants or moisture inside of the package, e.g. getters} - B81B 7/0058: {for protecting against damages due to external chemical or mechanical influences, e.g. shocks or vibrations} - B81C 1/00285: {using materials for controlling the level of pressure, contaminants or moisture inside of the package, e.g. getters} - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - B81B 2201/0264: Pressure sensors - B81B 2207/012: the micromechanical device and the control or processing electronics being separate parts in the same package - B81C 2203/0118: Bonding a wafer on the substrate, i.e. where the cap consists of another wafer - B81B: MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES (piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/00, H10N35/00) - B81C: PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS (making microcapsules or microballoons B01J13/02; processes or apparatus specially adapted for the manufacture or treatment of piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/01) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A packaged includes a flip-chip assembly. The flip-chip assembly includes a first semiconductor substrate having at least one integrated semiconductor device, and a second substrate connected to the first substrate. A main surface of the first semiconductor substrate faces and is spaced apart from the second substrate. The packaged semiconductor device further includes a parylene coating covering outer surfaces of the first semiconductor substrate and the second substrate. A first section of the main surface is exposed from the parylene coating. ## Claims ### Claim 1 A packaged semiconductor device, comprising: a flip-chip assembly, comprising a first semiconductor substrate comprising at least one integrated semiconductor device, and a second substrate connected to the first substrate, wherein a main surface of the first semiconductor substrate faces and is spaced apart from the second substrate; a parylene coating covering outer surfaces of the first semiconductor substrate and the second substrate, wherein a first section of the main surface is exposed from the parylene coating. ### Claim 2 (depends on 1) The packaged semiconductor device of claim 1, wherein only the first section of the main surface of the first semiconductor substrate is exposed from the parylene coating and every other surface of the first semiconductor substrate outside of the first section of the main surface is covered by the parylene coating. ### Claim 3 (depends on 2) The packaged semiconductor device of claim 2, wherein the first semiconductor substrate comprises a MEMs sensor device, and wherein a sensing portion of the MEMs sensor device is disposed in the first section of the main surface of the first semiconductor substrate. ### Claim 4 (depends on 3) The packaged semiconductor device of claim 3, wherein the MEMs sensor device comprises a pressure sensor configured to detect ambient air pressure at the main surface. ### Claim 5 (depends on 1) The packaged semiconductor device of claim 1, wherein the second semiconductor substrate comprises at least one integrated semiconductor device. ### Claim 6 (depends on 1) The packaged semiconductor device of claim 1, wherein the second semiconductor substrate is devoid of functional circuitry. ### Claim 7 (depends on 5) The packaged semiconductor device of claim 5, wherein the second semiconductor substrate is configured as a heat sink. ### Claim 8 (depends on 1) The packaged semiconductor device of claim 1, wherein the first semiconductor substrate is connected to the second semiconductor substrate by an interconnect structure, wherein the interconnect structure is completely covered by the parylene coating. ### Claim 9 (depends on 7) The packaged semiconductor device of claim 7, wherein the interconnect structure is a copper solder bump or stud. ### Claim 10 (depends on 1) The packaged semiconductor device of claim 1, further comprising a molded cavity package comprising an interior cavity and electrically conductive leads, wherein the flip-chip assembly is mounted within the interior cavity, and wherein the electrically conductive leads are connected to electrical terminals of the first semiconductor substrate. ### Claim 11 (depends on 9) The packaged semiconductor device of claim 9, wherein the electrically conductive leads are connected to electrical terminals of the first semiconductor substrate by one or more though-silicon-vias that extend through the second substrate. ### Claim 12 (depends on 9) The packaged semiconductor device of claim 9, wherein the electrically conductive leads are connected to electrical terminals of the first semiconductor substrate by one or more electrically conductive bond wires connected between the leads and electrical terminals of the of the second semiconductor substrate. ### Claim 13 (depends on 9) The packaged semiconductor device of claim 9, wherein the molded cavity package comprises an open side that extends between top ends of opposing outer sidewalls, and wherein the open side is covered by a gas-permeable membrane.