Combined low and high frequency continuous-time linear equalizers

An apparatus comprising:

• a power supply;
• a reference current source coupled to the power supply;
• a differential amplifier circuit comprising a first circuit branch and a second circuit branch connected to each other in parallel;
• a first transistor comprising a first gate, a first drain, and a gate-drain parasitic capacitance, the first drain is coupled to the first circuit branch;
• a second transistor comprising a second gate and a second drain, the second drain is coupled to the second circuit branch;
• a first resistor coupled to the first gate and comprising a first resistance based on the gate-drain parasitic capacitance;
• a second resistor coupled to the first resistor and the second gate such that the second resistor is positioned between the first resistor and the second gate;
• and
• a third transistor coupled to the reference current source, wherein the third transistor comprises a third gate, a third drain, and a third source, and wherein the third gate is connected to the third drain and coupled to a node between the first resistor and the second resistor.

An apparatus comprising:

• a differential amplifier circuit comprising a first circuit branch and a second circuit branch connected to each other in parallel;
• a first transistor comprising a first gate, a first drain, and a gate-drain parasitic capacitance, the first drain is coupled to the first circuit branch;
• a second transistor comprising a second gate and a second drain, the second drain is coupled to the second circuit branch;
• a first resistor coupled to the first gate and comprising a first resistance based on the gate-drain parasitic capacitance;
• and
• a second resistor coupled to the first resistor and the second gate such that the second resistor is positioned between the first resistor and the second gate,
• wherein the first circuit branch comprises:
• a power supply;
• an input terminal;
• an output terminal;
• an inductor coupled to the power supply;
• a third resistor coupled to the inductor;
• and
• a third transistor comprising a third drain coupled to the third resistor and the output terminal, a third gate coupled to the input terminal, and a third source coupled to the first drain.