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US 10,116,315 B1Granted
System-on-a-chip clock phase management using fractional-N PLLs
AssigneeQUALCOMM Incorporated
InventorsJingcheng Zhuang, Frederic Bossu
Life of this patent
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Abstract
A clock distribution architecture is provided in which the output clock signals from a plurality of fractional-N PLLs have a known phase relationship because each fractional-N PLL is configured to commence a phase accumulation responsive to a corresponding edge of a reference clock signal.
Claims17
A fractional-N phase-locked loop (PLL), comprising:
- a phase control circuit configured to begin a phase accumulation responsive to an identified edge of a reference clock signal, wherein the phase control circuit is configured to receive a trigger signal that identifies the identified edge of the reference clock signal;
- a feedback divider configured to divide an output clock signal by an integer divisor that is adjusted responsive to the phase accumulation to form a divided feedback clock signal;
- and
- an oscillator configured to drive the output clock signal at an output frequency responsive to a control signal so that the output clock signal is phase aligned with the reference clock signal.
1 more element
A method, comprising:
- receiving a trigger signal to identify an edge of a reference clock signal;
- beginning a phase accumulation responsive to the identified edge of the reference clock signal;
- and
- dividing an output clock signal for the first fractional-N PLL by a divisor that is adjusted responsive to the phase accumulation to form a divided feedback clock signal;
- and
- comparing the divided feedback clock signal to the reference clock signal to maintain a phase alignment of the output clock signal to the reference clock signal.
3 more elements
A fractional-N phase-locked loop (PLL), comprising:
- a phase control circuit configured to begin a phase accumulation responsive to an edge of a reference clock signal;
- means for producing an output clock signal having a frequency that is a non-integer multiple of a frequency for the reference clock signal responsive to the phase accumulation;
- a post divider for dividing the clock output signal to form a post-divided output clock output signal;
- and
- a digital phase corrector circuit configured to adjust the phase accumulation responsive to a phase of the post-divided output clock signal.
2 more elements
Dependencies are inferred from the claim text.