Multiple liner interconnects for three dimensional memory devices and method of making thereof

A method of forming a structure, comprising:

• forming at least one dielectric material layer over a substrate;
• forming an opening through the at least one dielectric material layer;
• forming a first metallic liner on a bottom surface and sidewalls of the opening by depositing a first metallic material;
• forming a metal portion consisting essentially of an elemental metal or an intermetallic alloy of at least two elemental metals on the first metallic liner;
• and
• forming a second metallic liner comprising a second metallic material directly on a top surface of the metal portion,
• wherein:
• the first metallic material and the second metallic material differ in composition;
• the first metallic liner and the second metallic liner contact an entirety of all surfaces of the metal portion;
• and
• the method comprises at least one feature selected from:
• a first feature that the method further comprises recessing a top surface of a topmost layer of the at least one dielectric material layer, wherein the second metallic liner is formed on upper portions of the sidewalls of the metal portion, and wherein the second metallic liner is deposited by a selective deposition process that deposits the second metallic material on metallic surfaces and does not deposit the second metallic material on dielectric surfaces;
• a second feature that the method further comprises recessing a top surface of a topmost layer of the at least one dielectric material layer, wherein the second metallic liner is formed on upper portions of the sidewalls of the metal portion, and wherein the metal portion comprises copper and the second metallic liner consists essentially of aluminum;
• or
• a third feature that the method further comprises:
• forming an alternating stack of insulating layers and electrically conductive word line layers of a three-dimensional NAND memory device over the substrate;
• forming memory stack structures through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film;
• at least partially removing a topmost portion of the at least one dielectric material layer below a horizontal plane including a top surface of the second metallic liner;
• and
• forming an air-gap dielectric layer including at least one cavity filled with vacuum or a gas phase material;
• wherein:
• the at least one dielectric material layer is formed over the alternating stack and the memory stack structures;
• the metal portion is electrically shorted to a drain region contacting an upper end of one of the vertical semiconductor channels;
• and
• the metal portion, the first metallic liner and the second metallic liner comprise a bit line of the three-dimensional NAND memory device.

A method of forming a structure, comprising:

• forming at least one dielectric material layer over a substrate;
• forming an opening through the at least one dielectric material layer;
• forming a first metallic liner on a bottom surface and sidewalls of the opening by depositing a first metallic material;
• forming a metal portion consisting essentially of an elemental metal or an intermetallic alloy of at least two elemental metals on the first metallic liner;
• recessing a top surface of a topmost layer of the at least one dielectric material layer;
• and
• forming a second metallic liner comprising a second metallic material directly on a top surface of the metal portion,
• wherein:
• the second metallic liner is formed on upper portions of the sidewalls of the metal portion;
• the first metallic material and the second metallic material differ in composition;
• the first metallic liner and the second metallic liner contact an entirety of all surfaces of the metal portion;
• and
• the second metallic liner is deposited on the top surface of the metal portion while the first metallic liner contacts an entirety of sidewalls of the metal portion;
• and
• wherein the method further comprises at least one feature selected from:
• a first feature that the metal portion is formed by depositing the metal or the intermetallic alloy in the opening and on the first metallic liner, by removing the metal or the intermetallic alloy from above a horizontal plane including a topmost surface of the at least one dielectric material layer, and by recessing the metal or the intermetallic alloy below the horizontal plane, and the second metallic liner is deposited by a non-selective deposition process that deposits the second metallic material, and by removing the second metallic material from above the horizontal plane;
• a second feature that the metal portion is formed by depositing the metal or the intermetallic alloy in the opening and on the first metallic liner, and by removing the metal or the intermetallic alloy from above a horizontal plane including a topmost surface of the at least one dielectric material layer, and the second metallic liner is deposited by a selective deposition process that deposits the second metallic material on metallic surfaces and does not deposit the second metallic material on dielectric surfaces;
• or
• a third feature that the metal portion comprises copper and the second metallic liner comprises a material selected from cobalt, cobalt-tungsten and cobalt-tungsten-phosphorus.