Spin transfer torque MRAM device with error buffer
AssigneeSpin Transfer Technologies, Inc.
InventorsBenjamin Stanley Louie, Neal Berger
Life of this patent
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Abstract
A nonvolatile error buffer is added to STT-MRAM memory design to reduce the error correction coding ECC required to achieve reliable operation with a non-zero Write Error Rate (“WER”). The error buffer is fully associative, storing both the address and the data of memory words which have failed to write correctly within an assigned ECC error budget. The write cycle includes a verify to determine if the word has been written correctly. The read cycle includes a search of the error buffer to determine if the address is present in the buffer.
Claims22
A random access memory (RAM) device, comprising
- a memory array comprised of an array of MRAM storage elements arranged as a plurality of data words, wherein each of the plurality of data words comprises an address;
- address and data lines, coupled to the memory array, wherein the data lines carry a data word to be written into the memory array and the address lines carry a corresponding address;
- a write buffer, coupled to the address and data lines, wherein the write buffer comprises a number of storage elements, and wherein the write buffer stores the data word and the corresponding address carried on the address and data lines during a write cycle;
- an error buffer, coupled to the write buffer, wherein the error buffer comprises a plurality of entries, wherein each of the error buffer entries comprises a plurality of storage elements and an associated buffer memory address;
- and
- a memory control logic that operates during a read cycle and the write cycle, wherein the memory control logic, during the write cycle, is operable to determine whether the data word was written into the memory array within a predefined error budget, and wherein the memory control logic writes the data word and the corresponding address from the write buffer into a selected one of the plurality of entries of the error buffer if the data word was not written into the memory array within the predefined error budget, and wherein the memory control logic, during a read cycle, is further operable to determine whether an address to be read is stored in the write buffer, the error buffer or the memory array.
A method for writing data into a memory device, the method comprising:
- writing a data word into memory cells of the memory device at a selected one of a plurality of memory addresses to store the data word in the memory device, wherein the memory device comprises the plurality of memory addresses, wherein each of the memory cells is operable to store a data word at a selected one of the plurality of memory addresses;
- storing the data word and the selected one of the plurality of memory addresses in a write buffer;
- reading the data word written to the memory device;
- comparing the data word written during the writing to the data word that was read during the reading;
- determining whether any differences from the comparing are within an allowable error budget;
- and
- if the differences are not within a predetermined error budget, writing the data word and the selected one of the plurality of memory addresses to a selected one of a plurality of buffer entries within an error buffer, wherein the writing comprises:
- determining which of the plurality of buffer entries is available for storing of the data word;
- selecting one of the plurality of buffer entries that is available for storing of the data word;
- and
- writing the data word into the buffer entry selected during the selecting;
- and
- while a first portion of the memory device is not undergoing either a write cycle or a read cycle, writing the data word stored in the selected one of the plurality of buffer entries within an error buffer into memory cells of the first portion of the memory device.
Dependencies are inferred from the claim text.