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US 10,114,796 B2Granted
Efficient implementation of cascaded biquads
AssigneeTexas Instruments Incorporated
InventorsAsheesh Bhardwaj, Lester A Longley
Life of this patent
Estimating the term…
Abstract
An improved biquad infinite impulse response filter is shown that may be implemented in a very large instruction word digital signal processor as well as in other processing circuitry. The new filter structure modifies the feedback path in the filter, resulting in a significant reduction in execution cycles.
Claims20
A infinite impulse response (IIR) filter comprising:
- an input terminal to receive an input signal;
- an output terminal to output an output signal;
- a first multiplier circuit to multiply the input signal by the sum of a first filter coefficient and a second filter coefficient to produce a first signal, the first multiplier circuit having an input to receive the input signal and an output to output the first signal;
- a second multiplier circuit to multiply the input signal by the sum of a third filter coefficient and a fourth filter coefficient to produce a second signal, the second multiplier circuit having an input to receive the input signal and an output to output the second signal;
- a third multiplier circuit to multiply a feedback signal by the first filter coefficient to produce a third signal, the third multiplier circuit having an input to receive the feedback signal and an output to output the third signal;
- a fourth multiplier circuit to multiply the feedback signal by the third filter coefficient to produce a fourth signal, the fourth multiplier circuit having an input to receive the feedback signal and an output to output the fourth signal;
- a first summing circuit to sum the second and fourth signals to produce a fifth signal, the first summing circuit having first and second inputs to receive the second and fourth signals, respectively, and an output to output the fifth signal;
- a first delay circuit to receive the fifth signal and apply a first delay thereto to produce a sixth signal, the first delay circuit having an input to receive the fifth signal and an output to output the sixth signal;
- a second summing circuit to sum the first, third, and sixth signals to produce a seventh signal, the second summing circuit having first, second, and third inputs to receive the first, third, and sixth signals, respectively, and an output to output the seventh signal;
- a second delay circuit to receive the seventh signal and apply a second delay thereto to produce an eighth signal, the second delay circuit having an input to receive the seventh signal and an output to output the eighth signal;
- and
- a third summing circuit to sum the input signal and the eighth signal to produce the output signal;
- wherein the eighth signal is the feedback signal.
10 more elements
A data processing device comprising:
- a infinite impulse response (IIR) filter comprising:
- an input terminal to receive an input signal;
- an output terminal to output an output signal;
- a first multiplier circuit to multiply the input signal by the sum of a first filter coefficient and a second filter coefficient to produce a first signal, the first multiplier circuit having an input to receive the input signal and an output to output the first signal;
- a second multiplier circuit to multiply the input signal by the sum of a third filter coefficient and a fourth filter coefficient to produce a second signal, the second multiplier circuit having an input to receive the input signal and an output to output the second signal;
- a third multiplier circuit to multiply a feedback signal by the first filter coefficient to produce a third signal, the third multiplier circuit having an input to receive the feedback signal and an output to output the third signal;
- a fourth multiplier circuit to multiply the feedback signal by the third filter coefficient to produce a fourth signal, the fourth multiplier circuit having an input to receive the feedback signal and an output to output the fourth signal;
- a first summing circuit to sum the second and fourth signals to produce a fifth signal, the first summing circuit having first and second inputs to receive the second and fourth signals, respectively, and an output to output the fifth signal;
- a first delay circuit to receive the fifth signal and apply a first delay thereto to produce a sixth signal, the first delay circuit having an input to receive the fifth signal and an output to output the sixth signal;
- a second summing circuit to sum the first, third, and sixth signals to produce a seventh signal, the second summing circuit having first, second, and third inputs to receive the first, third, and sixth signals, respectively, and an output to output the seventh signal;
- a second delay circuit to receive the seventh signal and apply a second delay thereto to produce an eighth signal, the second delay circuit having an input to receive the seventh signal and an output to output the eighth signal;
- and
- a third summing circuit to sum the input signal and the eighth signal to produce the output signal;
- wherein the eighth signal is the feedback signal.
11 more elements
A infinite impulse response (IIR) filter comprising:
- an input terminal to receive an input signal;
- an output terminal to output an output signal;
- a first multiplier circuit to multiply the input signal by the sum of a first filter coefficient and a second filter coefficient to produce a first signal, the first multiplier circuit having an input to receive the input signal and an output to output the first signal;
- a second multiplier circuit to multiply the input signal by the sum of a third filter coefficient and a fourth filter coefficient to produce a second signal, the second multiplier circuit having an input to receive the input signal and an output to output the second signal;
- a third multiplier circuit to multiply a feedback signal by the first filter coefficient to produce a third signal, the third multiplier circuit having an input to receive the feedback signal and an output to output the third signal;
- a fourth multiplier circuit to multiply the feedback signal by the third filter coefficient to produce a fourth signal, the fourth multiplier circuit having an input to receive the feedback signal and an output to output the fourth signal;
- a first summing circuit to sum the second and fourth signals to produce a fifth signal, the first summing circuit having first and second inputs to receive the second and fourth signals, respectively, and an output to output the fifth signal;
- a first delay circuit to receive the fifth signal and apply a first delay thereto to produce a sixth signal, the first delay circuit having an input to receive the fifth signal and an output to output the sixth signal;
- a second summing circuit to sum the first and sixth signals to produce a seventh signal, the second summing circuit having first and second inputs to receive the first and sixth signals, respectively, and an output to output the seventh signal;
- a third summing circuit to sum the third and seventh signals to produce an eighth signal, the third summing circuit having first and second inputs to receive the third and seventh signals, respectively, and an output to output the eighth signal;
- a second delay circuit to receive the eighth signal and apply a second delay thereto to produce a ninth signal, the second delay circuit having an input to receive the eighth signal and an output to output the ninth signal;
- and
- a fourth summing circuit to sum the input signal and the ninth signal to produce the output signal, the fourth summing circuit having first and second inputs to receive the input signal and the ninth signal, respectively, and an output to output the output signal;
- wherein the ninth signal is the feedback signal.
11 more elements
A data processing device comprising:
- a infinite impulse response (IIR) filter comprising:
- an input terminal to receive an input signal;
- an output terminal to output an output signal;
- a first multiplier circuit to multiply the input signal by the sum of a first filter coefficient and a second filter coefficient to produce a first signal, the first multiplier circuit having an input to receive the input signal and an output to output the first signal;
- a second multiplier circuit to multiply the input signal by the sum of a third filter coefficient and a fourth filter coefficient to produce a second signal, the second multiplier circuit having an input to receive the input signal and an output to output the second signal;
- a third multiplier circuit to multiply a feedback signal by the first filter coefficient to produce a third signal, the third multiplier circuit having an input to receive the feedback signal and an output to output the third signal;
- a fourth multiplier circuit to multiply the feedback signal by the third filter coefficient to produce a fourth signal, the fourth multiplier circuit having an input to receive the feedback signal and an output to output the fourth signal;
- a first summing circuit to sum the second and fourth signals to produce a fifth signal, the first summing circuit having first and second inputs to receive the second and fourth signals, respectively, and an output to output the fifth signal;
- a first delay circuit to receive the fifth signal and apply a first delay thereto to produce a sixth signal, the first delay circuit having an input to receive the fifth signal and an output to output the sixth signal;
- a second summing circuit to sum the first and sixth signals to produce a seventh signal, the second summing circuit having first and second inputs to receive the first and sixth signals, respectively, and an output to output the seventh signal;
- a third summing circuit to sum the third and seventh signals to produce an eighth signal, the third summing circuit having first and second inputs to receive the third and seventh signals, respectively, and an output to output the eighth signal;
- a second delay circuit to receive the eighth signal and apply a second delay thereto to produce a ninth signal, the second delay circuit having an input to receive the eighth signal and an output to output the ninth signal;
- and
- a fourth summing circuit to sum the input signal and the ninth signal to produce the output signal, the fourth summing circuit having first and second inputs to receive the input signal and the ninth signal, respectively, and an output to output the output signal;
- wherein the ninth signal is the feedback signal.
12 more elements
Dependencies are inferred from the claim text.