Dram architecture to reduce row activation circuitry power and peripheral leakage and related methods

A semiconductor device comprising:

• a plurality of volatile memory cells;
• peripheral circuitry coupled to the plurality of volatile memory cells and comprising a plurality of low threshold voltage (Vt) transistors configured to provide high speed operation during an active mode and a plurality of high Vt transistors configured as headers to reduce leakage in the low Vt transistors during a standby mode, the high Vt and low Vt transistors each comprising a superlattice, the superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions;
• a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during the active mode;
• and
• a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply the standby mode;
• wherein the peripheral circuitry comprises a sense amplifier;
• wherein the peripheral circuit circuitry is operable at a first clock rate during the first operating mode and a second clock rate lower than the first clock rate during the second operating mode, and wherein data stored in the plurality of volatile memory cells is fully refreshed during the second operating mode.

A method for making a semiconductor device comprising:

• forming a plurality of volatile memory cells;
• forming peripheral circuitry coupled to the plurality of volatile memory cells and comprising a plurality of low threshold voltage (Vt) transistors configured to provide high speed operation during a first operating mode and a plurality of high Vt transistors configured as headers to reduce leakage in the low Vt transistors during a second operating mode, the high Vt and low Vt transistors each comprising a superlattice, the superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions;
• forming a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during the first operating mode;
• and
• forming a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a the second operating mode;
• wherein the peripheral circuitry is operable at a first clock rate during the first operating mode and a second clock rate lower than the first clock rate during the second operating mode, and wherein data stored in the plurality of volatile memory cells is fully refreshed during the second operating mode.