Determining test conditions for at-speed transition delay fault tests on semiconductor devices

Non-transitory tangible computer readable media that includes instructions for execution, which when executed by a processor, performs operations comprising:

• analyzing scan patterns for testing a circuit of a device under test;
• identifying paths in the circuit that are activated by the scan patterns;
• determining behavior of the paths at different test corners;
• generating a histogram for each scan pattern, the histogram comprising a representation of a distribution of paths exhibiting worst-case behavior at corresponding test corners;
• generating an ordered set of scan pattern-test corner combinations based on the histogram;
• selecting a threshold for the ordered scan pattern-test corner combinations based on quality metrics, wherein the ordered scan pattern-test corner combinations above the threshold are associated with higher defect levels and the ordered scan pattern-test corner combinations below the threshold are associated with lower defect levels;
• and
• generating an ordered test set comprising the ordered scan pattern-test corner combinations with the selected threshold, wherein a test instrument tests the device under test according to the ordered test set, wherein the tests are performed at the test corners listed above the selected threshold using the corresponding scan patterns of the scan pattern-test corner combinations.

An apparatus, comprising:

• a memory element for storing data;
• and
• a processor, wherein the processor executes instructions associated with the data, wherein the processor and the memory element cooperate, such that the apparatus is configured for:
• analyzing scan patterns for testing a circuit of a device under test;
• identifying paths in the circuit that are activated by the scan patterns;
• determining behavior of the paths at different test corners;
• generating a histogram for each scan pattern, the histogram comprising a representation of a distribution of paths exhibiting worst-case behavior at corresponding test corners;
• generating an ordered set of scan pattern-test corner combinations based on the histogram;
• selecting a threshold for the ordered scan pattern-test corner combinations based on quality metrics, wherein the ordered scan pattern-test corner combinations above the threshold are associated with higher defect levels and the ordered scan pattern-test corner combinations below the threshold are associated with lower defect levels;
• generating an ordered test set comprising the ordered scan pattern-test corner combinations with the selected threshold;
• and
• feeding the ordered test set to a test instrument, wherein the test instrument tests the device under test according to the ordered test set, wherein the tests are performed at the test corners listed above the selected threshold using the corresponding scan patterns of the scan pattern-test corner combinations.