Semiconductor device including threshold voltage measurement circuitry

A semiconductor device comprising:

• a semiconductor wafer;
• a plurality of active circuitry areas spaced apart on the semiconductor wafer by scribe lines therebetween, each active circuitry area comprising a plurality of differential transistor pairs;
• and
• threshold voltage test circuitry on the substrate within at least one of the scribe lines and comprising
• a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, each test transistor having a respective input and output, and
• a plurality of gain stages configured to successively amplify the difference between the outputs of the differential test transistors over an input voltage range for measuring a threshold voltage thereof;
• wherein the plurality of differential transistor pairs and the pair of differential test transistors each comprises spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region;
• wherein each of the channel regions comprises a superlattice, the superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions.

A semiconductor device comprising:

• a substrate;
• active circuitry on the substrate and comprising a plurality of differential transistor pairs;
• and
• threshold voltage test circuitry on the substrate and comprising
• a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, each test transistor having a respective input and output, and
• at least one gain stage configured to amplify a difference between the outputs of the differential test transistors for measuring a threshold voltage thereof;
• wherein the plurality of differential transistor pairs and the pair of differential test transistors each comprises spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region;
• wherein each of the channel regions comprises a superlattice, the superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base silicon monolayers defining a base semiconductor silicon and at least one oxygen monolayer thereon constrained within a crystal lattice of adjacent base silicon portions.