Digital power multiplexor
AssigneeQUALCOMM Incorporated
InventorsVenkatasubramanian Narayanan, Dorav Kumar, Ramaprasath Vilangudipitchai, Venugopal Boynapalli
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Abstract
A power multiplexor includes: a first branch including a first transistor coupled in series with a second transistor between a first power supply and a power output; a second branch including a third transistor coupled in series with a fourth transistor between a second power supply and the power output; a controller configured to selectively assert and de-assert a control signal to the first branch and the second branch; a first voltage level shifter coupled between the second transistor and the controller; and a second voltage level shifter coupled between the third transistor and the controller.
Claims18
A power multiplexor comprising:
- a first branch including a first transistor coupled in series with a second transistor between a first power supply and a power output;
- a second branch including a third transistor coupled in series with a fourth transistor between a second power supply and the power output;
- a controller configured to selectively assert and de-assert a control signal to the first branch and the second branch;
- a first voltage level shifter coupled between the second transistor and the controller;
- and
- a second voltage level shifter coupled between the third transistor and the controller, wherein the first transistor is configured to receive the control signal from the controller at a voltage level of the first power supply, and wherein the first voltage level shifter is configured to increase a voltage of the control signal to a voltage level of the second power supply.
A method comprising:
- asserting a control signal to a first branch of a power multiplexor, the first branch including a first transistor and a second transistor coupled between a first power supply and a power output, wherein the control signal is applied to a gate of the first transistor and applied to a level shifter at a gate of the second transistor;
- de-asserting the control signal to a second branch of the power multiplexor, the second branch including a third transistor and a fourth transistor coupled between a second power supply and the power output;
- and
- conducting current from the second power supply to the power output after de-asserting the control signal to the second branch;
- wherein asserting the control signal to the first branch comprises:
- shifting a voltage of the control signal to a voltage associated with the second power supply by the level shifter, and applying the voltage associated with the second power supply to the gate of the second transistor.
A digital power multiplexor comprising:
- means for conducting current from a first power supply, the means for conducting current from the first power supply including a first transistor and a second transistor coupled in series between the first power supply and a power output;
- means for conducting current from a second power supply, the means for conducting current from the second power supply including a third transistor and a fourth transistor coupled in series between the second power supply and the power output;
- and
- means for selecting either the first power supply or the second power supply at a given time and not selecting the other of the first power supply or the second power supply at the given time, the means for selecting including control signal outputs to the first and fourth transistors and control signal outputs to voltage level shifters at the second and third transistors, wherein the first transistor is configured to receive a control signal from the selecting means at a voltage level of the first power supply, and wherein a first voltage level shifter coupled to the second transistor is configured to increase a voltage of the control signal to a voltage level associated with the second power supply.
Dependencies are inferred from the claim text.