US 10,103,122 B2Granted

Hybrid bonding systems and methods for semiconductor wafers

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsPing-Yin Liu, Shih-Wei Lin, Xin-Hua Huang, Lan-Lin Chao, Chia-Shiung Tsai

Life of this patent

Estimating the term…

Loading patent…

Abstract

Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.

Claims20

Dependent claims

A method comprising:

forming a first protection layer over at least a first contact pad of a first semiconductor wafer;
forming a second protection layer over at least a second contact pad of a second semiconductor wafer;
placing the first semiconductor wafer and the second semiconductor wafer in a first environment after forming the first protection layer and the second protection layer;
removing the first protection layer and the second protection layer while the first semiconductor wafer and the second semiconductor wafer are in a reduced oxygen environment, wherein an amount of oxygen in the reduced oxygen environment is lower than an amount of oxygen in the first environment;
coupling a top surface of the second semiconductor wafer to a top surface of the first semiconductor wafer while the first semiconductor wafer and the second semiconductor wafer are in the reduced oxygen environment;
and
bonding the first semiconductor wafer to the second semiconductor wafer while the first semiconductor wafer and the second semiconductor wafer are in the reduced oxygen environment.

4 more elements

A method comprising:

providing a first semiconductor wafer comprising a first plurality of conductive pads in a first insulating material on a top surface of the first plurality of conductive pads;
providing a second semiconductor wafer comprising a second plurality of conductive pads in a second insulating material on a top surface of the second plurality of conductive pads;
forming a first protection layer and a second protective layer on the first plurality of conductive pads and the second plurality of conductive pads, respectively, wherein the first protective layer and the second protective layer reduces oxidation of the first plurality of conductive pads and the second plurality of conductive pads;
removing the first protective layer and the second protection layer to expose the first plurality of conductive pads and the second plurality of conductive pads;
activating the top surfaces of the first semiconductor wafer and the second semiconductor wafer;
and
bonding the first semiconductor wafer to the second semiconductor wafer, wherein bonding the first semiconductor wafer to the second semiconductor wafer comprises:
forming a dielectric-to-dielectric bond between the first insulating material and the second insulating material;
and
forming a metal-to-metal bond between the first plurality of conductive pads and the second plurality of conductive pads.

7 more elements

A method comprising:

forming a first protection layer over a first top surface of a first semiconductor wafer, the first semiconductor wafer comprising a first conductive pad disposed in a first insulating material at the first top surface;
placing the first semiconductor wafer and a second semiconductor wafer into a reduced oxygen environment, wherein the second semiconductor wafer comprises a second conductive pad disposed in a second insulating material at a second top surface of the second semiconductor wafer;
removing the first protection layer from over the first top surface of the first semiconductor wafer;
removing a conductive oxide at a top surface of the first conductive pad;
and
bonding the first semiconductor wafer to the second semiconductor wafer, wherein removing the first protection layer, removing the conductive oxide at the first top surface to the second top surface, and bonding the first semiconductor wafer to the second semiconductor wafer are performed without removing the first semiconductor wafer and the second semiconductor wafer from the reduced oxygen environment, and wherein bonding the first semiconductor wafer to the second semiconductor wafer comprises:
forming a bonding interface between the first conductive pad and the second conductive pad;
and
forming a bonding interface between the first insulating material and the second insulating material.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/689,982Filed 29 Aug 2017 · continuation
Priority: 5 Jul 2012
Published: US 2017/0358551 A114 Dec 2017
Granted: 16 Oct 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification28 codes

H10W 72/013
Manufacture or treatment: of die-attach connectors
H10W 72/01953
Changing the shapes of bond pads: by etching
H10W 72/01971
Of bond pads: cleaning, e.g. oxide removal
H10W 72/0198
Manufacture or treatment: batch processes

Family

Application13/542,507Parent of this continuation · filed 5 Jul 2012
Application14/725,266Parent of this continuation · filed 29 May 2015
US 9,048,283 B2Parent of this continuation · filed 2 Jun 2015
US 2017/0358551 A1Pre-grant publication · published 14 Dec 2017
US 9,748,198 B2Parent of this continuation
US 2014/0011324 A1Published application
US 2015/0287694 A1Published application
US 10,103,122 B2This patent

From the US filing history. Foreign family members aren’t listed.