System and method for generating cross-core breakpoints in a multi-core microcontroller

An integrated circuit device comprising a plurality of microcontrollers operating independently from each other, the integrated circuit further comprising:

• a first microcontroller of said plurality of microcontrollers comprising a first processor core, associated first program memory and first emulator logic for activating a first processor core breakpoint, the first microcontroller further comprising a plurality of first peripheral devices, wherein one of the first peripheral devices is a serial communication peripheral;
• a breakpoint register within the first microcontroller and coupled with said first processor core for configuring a debugging breakpoint in the first processor core comprising at least one bit for enabling a cross breakpoint;
• a second microcontroller of said plurality of microcontrollers comprising a second processor core communicatively coupled to the first processor core and including second emulator logic, wherein the second microcontroller comprises second program memory associated with the second processor core and a plurality of second peripheral devices, wherein one of the second peripheral devices is a serial communication peripheral;
• and
• a first cross breakpoint logic within the first emulator logic which, when said at least one bit is set, is configured to communicate a cross breakpoint signal by the first emulator logic at the first processor core to the second processor core thereby stopping execution of instructions in the second processor core.