Data processor

A processor comprising:

• a first-receiver-node for receiving a first-receiver-signal;
• a second-receiver-node for receiving a second-receiver-signal;
• a first-output-node for coupling to a digital-baseband-processor;
• a second-output-node for coupling to the digital-baseband-processor;
• a first-active-data-pipe extending between the first-receiver-node and the first-output-node, the first-active-data-pipe comprising:
• a first-analogue-to-digital-converter comprising
• a first-ADC-input coupled to the first-receiver-node;
• and
• a first-ADC-output coupled to the first-output-node;
• wherein the first-analogue-to-digital-converter is configured to provide a first-digital-signal to the first-output-node;
• a first-reference-node associated with the first-active-data-pipe;
• and
• a configurable-data-pipe extending between the second-receiver-node and the second-output-node, the configurable-data-pipe comprising:
• a configurable-pipeline-multiplexer comprising:
• a first-MUX-input-node coupled to the second-receiver-node;
• a second-MUX-input-node coupled to the first-reference-node;
• and
• a MUX-output-node;
• and
• a second-analogue-to-digital-converter comprising:
• a second-ADC-input coupled to the MUX-output-node;
• and
• a second-ADC-output coupled to the second-output-node,
• wherein, when the configurable-pipeline-multiplexer is configured to couple the second-MUX-input-node to the MUX-output-node, the second-analogue-to-digital-converter is configured to provide a first-digital-reference-signal to the second-output-node.