Digital output binning
AssigneeSensors Unlimited, Inc.
InventorJoshua Lund
Life of this patent
Estimating the term…
Abstract
An imaging system includes a readout integrated circuit (ROIC) is operatively connected to receive photocurrent from a plurality of photodetectors (e.g., from a plurality of photodetectors of a photodetector array (PDA)). An event detection circuit in each ROIC pixel readout circuit generates binary output data, wherein the ROIC compresses the binary output data with a logical summary binning of N×M pixel binary outputs into a single summary output bit. The ROIC can be configured to receive image data from the photodetectors to form an image at a first frame rate, and to receive the binned binary data from the photodetectors at a second frame rate higher than the first frame rate.
Claims14
An imaging system comprising:
- a readout integrated circuit (ROIC) operatively connected to receive photocurrent from a plurality of photodetectors;
- and
- an event detection circuit in each ROIC pixel readout circuit for generating binary output data, wherein the ROIC is configured to compress the binary output data with a logical summary binning of N×M pixel binary outputs into a single summary output bit, wherein the ROIC is configured to receive non-binary image data from the photodetectors to form an image at a first frame rate, and to receive the binned binary data from the photodetectors at a second frame rate higher than the first frame rate.
An imaging system comprising:
- a readout integrated circuit (ROIC) operatively connected to receive photocurrent from a plurality of photodetectors;
- and
- an event detection circuit in each ROIC pixel readout circuit for generating binary output data, wherein the ROIC is configured to compress the binary output data with a logical summary binning of N×M pixel binary outputs into a single summary output bit, wherein the ROIC includes logic to perform a logical OR function on each N×M sub-array of pixels to indicate if any pixels in the sub-array represent a logic high, wherein the ROIC includes logic to generate a summary bit representing a logical high for the entire sub-array if any of the pixels in the sub-array represent a logic high, and representing a logic low for the entire sub-array if any of the pixels in the sub-array represent a logic low, and to output the summary bit for each sub-array, realizing a compression rate of N×M to 1.
An imaging system comprising:
- a readout integrated circuit (ROIC) operatively connected to receive photocurrent from a plurality of photodetectors;
- and
- an event detection circuit in each ROIC pixel readout circuit for generating binary output data, wherein the ROIC is configured to compress the binary output data with a logical summary binning of N×M pixel binary outputs into a single summary output bit, wherein the ROIC includes logic to perform a logical OR function on each N×M sub-array of pixels to indicate if any pixels in the sub-array represent a logic high, wherein the ROIC includes logic for combining multiple pixels in a column during readout by selecting multiple rows of pixels in the FPA, simultaneously connecting them to the column, wherein the ROIC includes a respective pulldown circuit for each pixel, and wherein the ROIC includes a respective common pull-up circuit for each column, in a wired-OR architecture.
Dependencies are inferred from the claim text.