High speed DFEs with direct feedback

A method of equalizing in a decision feedback equalizer having a plurality of paths, the method comprising:

• receiving, by a plurality of adder circuits, a digital code representing a previously decided symbol from an output of a prior path of the plurality of paths, wherein each adder circuit receives a respective bit of the digital code;
• receiving, by a decision-making slicer circuit, an input voltage;
• receiving, by the decision-making slicer circuit, a first clock signal operative to initiate a decision-making phase of the decision-making slicer circuit;
• receiving, by the plurality of adder circuits, a second clock signal operative to initiate an injection of an offset current into a current injection input of the decision-making slicer circuit;
• injecting, by the plurality of adder circuits, the offset current proportional to the digital code representing the previously decided symbol into the current injection input, at a first edge of the second clock signal;
• and
• introducing a predetermined skew between the first clock signal and the second clock signal.

A decision feedback equalizer (DFE), comprising:

• a plurality of paths, each path having at least one adding slicer comprising:
• a decision-making slicer circuit comprising a first input, a second input coupled to a first clock signal that initiates a decision-making phase of the decision-making slicer circuit at a first edge of the first clock signal, an output, and a current injection input;
• and
• an adder circuit having an input operative to receive a respective bit of a digital code representing a previously decided symbol, fed back from an output of a prior path of the plurality of paths, and an input coupled to a second clock signal, wherein:
• the adder circuit is configured to inject an offset current proportional to the digital code representing the previously decided symbol into the current injection input at a first edge of the second clock signal, and
• there is a predetermined skew between the first clock signal and the second clock signal to control a timing between the injection of the offset current of the adder circuit and the initiation of the decision-making phase of the decision-making slicer circuit.