Secure hash algorithm in digital hardware for cryptographic applications

A digital circuit for generating a hash of a message using a secure hashing algorithm, the digital circuit comprising:

• a plurality of expansion circuits, each expansion circuit configured to receive at least a portion of the message and generate first and second expanded message blocks based on an expansion function applied to the portion of the message;
• a plurality of pipelined compression circuits, each compression circuit corresponding to an expansion circuit and configured to receive the first and second expanded message blocks generated by the corresponding expansion circuit and a plurality of initial hash variables associated with a first round of compression, said each compression circuit comprising:
• first compression logic configured to receive the plurality of initial hash variables and a first expanded message block and generate a plurality of intermediary working variables including a first intermediary working variable, a second intermediary working variable, and a third intermediary working variable, by applying a compression function to the plurality of initial hash variables and the first expanded message block, the plurality of intermediary working variables associated with a second round of compression;
• and
• second compression logic coupled to the first compression logic and configured to receive the second expanded message block and the second and the third intermediary working variables, and generate a plurality of output hash variables associated with a third round of compression by applying the compression function to the second expanded message block and the second and the third intermediary working variables, the output hash variables provided as input to a next compression module in the plurality of pipelined compression modules.