Testing of clock and data recovery circuits

A method of operation in a device that comprises a clock data recovery (CDR) circuit having an input node, an output node and a data recovery circuit, the CDR circuit supporting a first mode and a second mode of operation, the method comprising:

• in the first mode:
• receiving an input data signal at the input node;
• providing the input data signal at the input node to an input of the data recovery circuit, the data recovery circuit recovering first data from the input data signal;
• and
• providing the first data to the output node;
• and
• in the second mode:
• generating a test data pattern which is provided to the output node;
• looping back the test data pattern from the output node to the input of the data recovery circuit, the data recovery circuit recovering second data from the test data pattern, and
• checking the second data for errors.

A method of performing a system level test in a system that comprises a first clock and data recovery (CDR) circuit of a first communication device and a second CDR circuit of a second communication device, the method comprising:

• generating a test data pattern by the first CDR circuit;
• transmitting the test data pattern from the first communication device to the second communication device;
• recovering, by a data recovery circuit of the second CDR circuit, data from the test data pattern;
• checking, by a test circuit of the second CDR circuit, the recovered data for errors;
• and
• generating a test result signal indicating whether the system level test has passed or failed based on whether errors are detected in the recovered data.