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US 10,097,273 B2Granted
High-speed receiver architecture
AssigneeInphi Corporation
InventorsOscar Ernesto Agazzi, Diego Ernesto Crivelli, Hugo Santiago Carrer, Mario Rafael Hueda, German Cesar Augusto Luna, Carl Grace
Life of this patent
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Abstract
A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.
Claims22
A receiver comprising:
- an analog-to-digital converter (ADC) that generates signal samples from a received signal having combined non-Gaussian noise and Gaussian noise;
- wherein the ADC is a pipelined ADC including an input track-and-hold stage followed by a plurality of low resolution ADC stages, each ADC stage including
- a 1-bit comparator coupled to the input track-and-hold stage,
- a 1-bit digital-to-analog converter (DAC) coupled to the 1-bit comparator,
- an analog subtractor coupled to the 1-bit DAC and the input track-and-hold stage,
- a residue amplifier coupled to the analog subtractor, and
- a track-and-hold circuit coupled to the residue amplifier;
- a feedforward equalizer coupled to receive the signal samples from the ADC, and to apply equalization to generate equalized samples;
- a decoder coupled to an output of the feedforward equalizer, the decoder determining detected symbols from the equalized samples and a channel model by minimizing a cumulative metric that compensates the combined Gaussian and non-Gaussian noise in the received signal;
- and
- a channel estimator to receive the output of the feedforward equalizer and an output of the decoder and to generate the channel model and an error feedback signal to adaptively update coefficients of the feedforward equalizer based on the error feedback signal;
- wherein the ADC is configured in a sub-radix architecture having more ADC stages than there are bits in the received signal.
9 more elements
A receiver comprising:
- an analog-to-digital converter (ADC) that generates signal samples from a received signal having combined non-Gaussian noise and Gaussian noise;
- wherein the ADC is a pipelined ADC including an input track-and-hold stage followed by a plurality of low resolution ADC stages, each ADC stage including
- a 1-bit comparator coupled to the input track-and-hold stage,
- a 1-bit digital-to-analog converter (DAC) coupled to the 1-bit comparator,
- an analog subtractor coupled to the 1-bit DAC and the input track-and-hold stage,
- a residue amplifier coupled to the analog subtractor, and
- a track-and-hold circuit coupled to the residue amplifier;
- a feedforward equalizer coupled to receive the signal samples from the ADC, and to apply equalization to generate equalized samples;
- a decoder coupled to an output of the feedforward equalizer, the decoder determining detected symbols from the equalized samples and a channel model by minimizing a cumulative metric that compensates the combined Gaussian and non-Gaussian noise in the received signal;
- and
- a channel estimator to receive the output of the feedforward equalizer and an output of the decoder and to generate the channel model and an error feedback signal to adaptively update coefficients of the feedforward equalizer based on the error feedback signal;
- wherein the cumulative metric is approximated by
- M≈Σn[(ŷn)v−(ŝn)v]2 where M is the cumulative metric, ŷn represents a sample at the output of the feedforward equalizer, ŝn is a noise-free signal component of ŷn, where 0<v≤1.
10 more elements
A receiver comprising:
- an analog-to-digital converter (ADC) that generates signal samples from a received signal having combined non-Gaussian noise and Gaussian noise;
- wherein the ADC is a pipelined ADC including an input track-and-hold stage followed by a plurality of low resolution ADC stages, each ADC stage including
- a 1-bit comparator coupled to the input track-and-hold stage,
- a 1-bit digital-to-analog converter (DAC) coupled to the 1-bit comparator,
- an analog subtractor coupled to the 1-bit DAC and the input track-and-hold stage,
- a residue amplifier coupled to the analog subtractor, and
- a track-and-hold circuit coupled to the residue amplifier;
- a feedforward equalizer coupled to receive the signal samples from the ADC, and to apply equalization to generate equalized samples;
- a decoder coupled to an output of the feedforward equalizer, the decoder determining detected symbols from the equalized samples and a channel model by minimizing a cumulative metric that compensates the combined Gaussian and non-Gaussian noise in the received signal;
- and
- a channel estimator to receive the output of the feedforward equalizer and an output of the decoder and to generate the channel model and an error feedback signal to adaptively update coefficients of the feedforward equalizer based on the error feedback signal;
- wherein the ADC further includes a look-up table (LUT) configured to the plurality of ADC stages to store the inverses of non-linear characteristics of the signal samples.
9 more elements
A receiver comprising:
- an analog-to-digital converter (ADC) that generates signal samples from a received signal having combined non-Gaussian noise and Gaussian noise;
- wherein the ADC is a pipelined ADC including an input track-and-hold stage followed by a plurality of low resolution ADC stages, each ADC stage including
- a 1-bit comparator coupled to the input track-and-hold stage,
- a 1-bit digital-to-analog converter (DAC) coupled to the 1-bit comparator,
- an analog subtractor coupled to the 1-bit DAC and the input track-and-hold stage,
- a residue amplifier coupled to the analog subtractor, and
- a track-and-hold circuit coupled to the residue amplifier;
- a feedforward equalizer coupled to receive the signal samples from the ADC, and to apply equalization to generate equalized samples;
- a decoder coupled to an output of the feedforward equalizer, the decoder determining detected symbols from the equalized samples and a channel model by minimizing a cumulative metric that compensates the combined Gaussian and non-Gaussian noise in the received signal;
- and
- a channel estimator to receive the output of the feedforward equalizer and an output of the decoder and to generate the channel model and an error feedback signal to adaptively update coefficients of the feedforward equalizer based on the error feedback signal;
- wherein the ADC further includes a lookahead pipeline configuration in which one or more of the plurality of ADC stages includes a pair of comparators configured to enable parallel interstage amplification and comparator operations.
9 more elements
A method for equalizing a received signal, the method comprising:
- generating, by an analog-to-digital converter (ADC), signal samples from the received signal having combined non-Gaussian noise and Gaussian noise;
- wherein the ADC is a pipelined ADC including an input track-and-hold stage followed by a plurality of low resolution ADC stages, each ADC stage including
- a 1-bit comparator coupled to the input track-and-hold stage,
- a 1-bit digital-to-analog converter (DAC) coupled to the 1-bit comparator,
- an analog subtractor coupled to the 1-bit DAC and the input track-and-hold stage,
- a residue amplifier coupled to the analog subtractor, and
- a track-and-hold circuit coupled to the residue amplifier;
- wherein generating signal samples by the ADC includes generating 1-bit of each sample through each of the ADC stages according to the following:
- determining, by the comparator, a contribution voltage from the received signal;
- developing, by the analog subtractor, a residue by subtracting the contribution voltage from the received signal;
- multiplying, by the residue amplifier, the residue by a gain value;
- and
- holding, by the track-and-hold circuit, the residue;
- applying, by a feedforward equalizer, an equalization to the signal samples from the ADC to generate equalized samples;
- determining, by a decoder coupled to an output of the feedforward equalizer, detected symbols from the equalized samples and a channel model by minimizing a cumulative metric that compensates the combined Gaussian and non-Gaussian noise in the received signal;
- and
- generating, by a channel estimator, the channel model and an error feedback signal to adaptively update coefficients of the feedforward equalizer based on the error feedback signal.
14 more elements
A transceiver chip for communication over an optical fiber, the transceiver chip comprising:
- a host interface for providing encoded data in a host format for transmitting over the optical fiber and for receiving decoded data in the host format originating from the optical fiber;
- transmit path circuitry to receive the encoded data from the host interface and generate an electrical signal suitable for driving a laser coupled to the optical fiber;
- an input port for receiving a received signal originating from the optical fiber having combined non-Gaussian noise and Gaussian noise;
- and
- receive path circuitry coupled between the input port and the host interface, the receive path circuitry comprising:
- an analog-to-digital converter (ADC) that generates signal samples from the received signal having the combined non-Gaussian noise and Gaussian noise;
- wherein the ADC is a pipelined ADC including an input track-and-hold stage followed by a plurality of low resolution ADC stages, each ADC stage including
- a 1-bit comparator coupled to the input track-and-hold stage,
- a 1-bit digital-to-analog converter (DAC) coupled to the 1-bit comparator,
- an analog subtractor coupled to the 1-bit DAC and the input track-and-hold stage,
- a residue amplifier coupled to the analog subtractor, and
- a track-and-hold circuit coupled to the residue amplifier;
- a feedforward equalizer coupled to receive the signal samples from the ADC, and to apply equalization to generate equalized samples;
- a decoder coupled to an output of the feedforward equalizer, the decoder determining detected symbols from the equalized samples and a channel model by minimizing a cumulative metric that compensates the combined Gaussian and non-Gaussian noise in the received signal, the decoder to generate the decoded data;
- and
- a channel estimator to receive the output of the feedforward equalizer and an output of the decoder and to generate the channel model and an error feedback signal to adaptively update coefficients of the feedforward equalizer based on the error feedback signal;
- wherein the ADC is configured in a sub-radix architecture having more ADC stages than there are bits in the received signal.
14 more elements
A transceiver chip for communication over an optical fiber, the transceiver chip comprising:
- a host interface for providing encoded data in a host format for transmitting over the optical fiber and for receiving decoded data in the host format originating from the optical fiber;
- transmit path circuitry to receive the encoded data from the host interface and generate an electrical signal suitable for driving a laser coupled to the optical fiber;
- an input port for receiving a received signal originating from the optical fiber having combined non-Gaussian noise and Gaussian noise;
- and
- receive path circuitry coupled between the input port and the host interface, the receive path circuitry comprising:
- an analog-to-digital converter (ADC) that generates signal samples from the received signal having the combined non-Gaussian noise and Gaussian noise;
- wherein the ADC is a pipelined ADC including an input track-and-hold stage followed by a plurality of low resolution ADC stages, each ADC stage including
- a 1-bit comparator coupled to the input track-and-hold stage,
- a 1-bit digital-to-analog converter (DAC) coupled to the 1-bit comparator,
- an analog subtractor coupled to the 1-bit DAC and the input track-and-hold stage,
- a residue amplifier coupled to the analog subtractor, and
- a track-and-hold circuit coupled to the residue amplifier;
- a feedforward equalizer coupled to receive the signal samples from the ADC, and to apply equalization to generate equalized samples;
- a decoder coupled to an output of the feedforward equalizer, the decoder determining detected symbols from the equalized samples and a channel model by minimizing a cumulative metric that compensates the combined Gaussian and non-Gaussian noise in the received signal, the decoder to generate the decoded data;
- and
- a channel estimator to receive the output of the feedforward equalizer and an output of the decoder and to generate the channel model and an error feedback signal to adaptively update coefficients of the feedforward equalizer based on the error feedback signal;
- wherein the cumulative metric is approximated by
- M≈Σn[(ŷn)v−(ŝn)v]2 where M is the cumulative metric, ŷn represents a sample at the output of the feedforward equalizer, ŝn is a noise-free signal component of ŷn, where 0<v≤1.
15 more elements
A transceiver chip for communication over an optical fiber, the transceiver chip comprising:
- a host interface for providing encoded data in a host format for transmitting over the optical fiber and for receiving decoded data in the host format originating from the optical fiber;
- transmit path circuitry to receive the encoded data from the host interface and generate an electrical signal suitable for driving a laser coupled to the optical fiber;
- an input port for receiving a received signal originating from the optical fiber having combined non-Gaussian noise and Gaussian noise;
- and
- receive path circuitry coupled between the input port and the host interface, the receive path circuitry comprising:
- an analog-to-digital converter (ADC) that generates signal samples from the received signal having the combined non-Gaussian noise and Gaussian noise;
- wherein the ADC is a pipelined ADC including an input track-and-hold stage followed by a plurality of low resolution ADC stages, each ADC stage including
- a 1-bit comparator coupled to the input track-and-hold stage,
- a 1-bit digital-to-analog converter (DAC) coupled to the 1-bit comparator,
- an analog subtractor coupled to the 1-bit DAC and the input track-and-hold stage,
- a residue amplifier coupled to the analog subtractor, and
- a track-and-hold circuit coupled to the residue amplifier;
- a feedforward equalizer coupled to receive the signal samples from the ADC, and to apply equalization to generate equalized samples;
- a decoder coupled to an output of the feedforward equalizer, the decoder determining detected symbols from the equalized samples and a channel model by minimizing a cumulative metric that compensates the combined Gaussian and non-Gaussian noise in the received signal, the decoder to generate the decoded data;
- and
- a channel estimator to receive the output of the feedforward equalizer and an output of the decoder and to generate the channel model and an error feedback signal to adaptively update coefficients of the feedforward equalizer based on the error feedback signal;
- wherein the ADC further includes a look-up table (LUT) configured to the plurality of ADC stages to store the inverses of non-linear characteristics of the signal samples.
14 more elements
A transceiver chip for communication over an optical fiber, the transceiver chip comprising:
- a host interface for providing encoded data in a host format for transmitting over the optical fiber and for receiving decoded data in the host format originating from the optical fiber;
- transmit path circuitry to receive the encoded data from the host interface and generate an electrical signal suitable for driving a laser coupled to the optical fiber;
- an input port for receiving a received signal originating from the optical fiber having combined non-Gaussian noise and Gaussian noise;
- and
- receive path circuitry coupled between the input port and the host interface, the receive path circuitry comprising:
- an analog-to-digital converter (ADC) that generates signal samples from the received signal having the combined non-Gaussian noise and Gaussian noise;
- wherein the ADC is a pipelined ADC including an input track-and-hold stage followed by a plurality of low resolution ADC stages, each ADC stage including
- a 1-bit comparator coupled to the input track-and-hold stage,
- a 1-bit digital-to-analog converter (DAC) coupled to the 1-bit comparator,
- an analog subtractor coupled to the 1-bit DAC and the input track-and-hold stage,
- a residue amplifier coupled to the analog subtractor, and
- a track-and-hold circuit coupled to the residue amplifier;
- a feedforward equalizer coupled to receive the signal samples from the ADC, and to apply equalization to generate equalized samples;
- a decoder coupled to an output of the feedforward equalizer, the decoder determining detected symbols from the equalized samples and a channel model by minimizing a cumulative metric that compensates the combined Gaussian and non-Gaussian noise in the received signal, the decoder to generate the decoded data;
- and
- a channel estimator to receive the output of the feedforward equalizer and an output of the decoder and to generate the channel model and an error feedback signal to adaptively update coefficients of the feedforward equalizer based on the error feedback signal;
- wherein the ADC further includes a lookahead pipeline configuration in which one or more of the plurality of ADC stages includes a pair of comparators configured to enable parallel interstage amplification and comparator operations.
14 more elements
Dependencies are inferred from the claim text.