Lane-striped computation of packet CRC to maintain burst error properties
AssigneeNVIDIA Corporation
InventorsEric Tyson, Stephen D. Glaser, Mike Osborn, Mark Hummel
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Abstract
A CRC generator, a method for computing a CRC of a data packet, and an electronic system, such as a circuit board, are disclosed herein. In one embodiment the method is for computing the CRC of a data packet to be transmitted on a serial communications link having multiple lanes. In one embodiment, the CRC generator includes: (1) a CRC calculator configured to define a CRC calculation of a data packet in sequential order and perform parallelized computations, according to the sequential order and the multiple lanes, to generate sub-CRC values and (2) combination circuitry configured to combine the sub-CRC values to provide the CRC value for the packet.
Claims20
A cyclic redundancy check (CRC) generator of a serial communications link having multiple lanes, comprising:
- a CRC calculator configured to define a CRC calculation of a data packet, for transmission on said multiple lanes, in sequential order and to perform parallelized computations on each lane of said multiple lanes based on said sequential order to generate sub-CRC values;
- and
- combination circuitry configured to combine said sub-CRC values to provide a final packet CRC value for said packet that maintains sequential error detection for said packet over said transmission on said multiple lanes.
A method for transmitting a data packet on a serial communications link having multiple lanes, comprising:
- defining a calculation for a cyclic redundancy check (CRC) value of a data packet in sequential order;
- calculating, in parallel, a sub-CRC value of said CRC value for each lane of said multiple lanes;
- and
- generating said CRC value for said data packet based on a combination of each said sub-CRC value, wherein said CRC value maintains sequential error detection for transmitting said data packet on said multiple lanes.
A circuit board, comprising:
- a first device;
- a second device;
- and
- a serial communications link having multiple lanes communicatively coupling said first device to said second device, said serial communications link including a transmitter having a cyclic redundancy check (CRC) generator comprising:
- a CRC calculator configured to define, in sequential order, a CRC of a data packet to transmit over said multiple lanes and to perform parallelized computations on each of said multiple lanes based on said sequential order to generate sub-CRC values;
- and
- combination circuitry configured to combine said sub-CRC values to provide a final packet CRC value for said data packet that maintains sequential error detection for said data packet in transmissions over said serial communications link.
Dependencies are inferred from the claim text.