Back to results
US 10,097,198 B1Granted
Sar adc
AssigneesSK hynix Inc., Sogang University Research Foundation
InventorsSeung Hoon Lee, Hee Wook Shin, Eun Chang Lee
Life of this patent
Estimating the term…
Abstract
Disclosed is a successive-approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC may include a capacitor-resistor hybrid digital-to-analog converter (DAC), and apply a low-power switching method and an input signal range scaling method to the DAC, thereby significantly reducing surface area and power consumption.
Claims17
A successive-approximation register (SAR) analog-to-digital converter (ADC) comprising:
- a digital-to-analog converter (DAC),
- wherein the DAC comprises:
- a first capacitor array comprising a plurality of first capacitors;
- a second capacitor array comprising a plurality of second capacitors;
- and
- a resistor string suitable for generating differential reference voltages,
- wherein the SAR ADC determines a digital code of high-order bits by selectively applying first and second reference voltages and an input signal to the first capacitors, and
- wherein the SAR ADC determines a digital code of low-order bits by selectively applying the differential reference voltages and a common mode voltage to the second capacitors,
- wherein when sampling the input signal, the SAR ADC applies the common mode voltage to top plates of the first and second capacitors, applies the input signal to bottom plates of the first capacitors, applies the common mode voltage to bottom plates of the capacitors corresponding to the least significant bits, and applies the input signal to bottom plates of capacitors corresponding to most significant bits among the second capacitors.
6 more elements
A successive-approximation register (SAR) analog-to-digital converter (ADC) comprising:
- a digital-to-analog converter (DAC) comprising a first capacitor array including a plurality of first capacitors, a second capacitor array including a plurality of second capacitors, and a resistor string suitable for providing differential reference voltages;
- a comparator suitable for comparing output signals of the DAC;
- and
- a SAR logic circuit suitable for converting an input signal into a digital code using the comparison result,
- wherein the SAR logic circuit determines a digital code of high-order bits by selectively applying first and second reference voltages and an input signal to the first capacitors, and
- wherein the SAR logic circuit determines a digital code of low-order bits by selectively applying the differential reference voltages and a common mode voltage to the second capacitors,
- wherein when the input signal is sampled, the SAR logic circuit applies the common mode voltage to top plates of the first and second capacitors, applies the input signal to bottom plates of the first capacitors, applies the common mode voltage to bottom plates of capacitors corresponding to least significant bits among the second capacitors, and applies the input signal to bottom plates of capacitors corresponding to most significant bits among the second capacitors.
4 more elements
A successive-approximation register (SAR) analog-to-digital converter (ADC) comprising:
- a digital-to-analog converter (DAC),
- wherein the DAC comprises:
- a first capacitor array comprising first capacitors of which the capacities have a ratio of powers of 2;
- a second capacitor array comprising a plurality of second capacitors each of which is a unit capacitor;
- and
- a resistor string suitable for generating differential reference voltages including levels which have a ratio of powers of 2, in the range of first and second reference voltages,
- wherein the first capacitors and a part of the second capacitors are configured to sample the input signal,
- wherein when sampling the input signal, the SAR ADC applies the common mode voltage to top plates of the first and second capacitors, applies the input signal to bottom plates of the first capacitors, applies the common mode voltage to bottom plates of capacitors corresponding to least significant bits among the second capacitors, and applies the input signal to bottom plates of capacitors corresponding to most significant bits among the second capacitors.
5 more elements
Dependencies are inferred from the claim text.