Wide capture range reference-less frequency detector

A clock/data recovery system, comprising:

• a voltage controlled oscillator configured to generate a clock signal;
• a phase detector coupled to the voltage controlled oscillator and configured to generate a buffered data signal and a phase difference control signal based on an input data signal and the clock signal, wherein the phase difference control signal is indicative of a phase difference between the clock signal and the input data signal;
• a reference-less frequency detector coupled to the voltage controlled oscillator and configured to generate a frequency difference control signal indicative of a frequency difference between the input data signal and the clock signal, the reference-less frequency detector comprising:
• a sampling circuit configured to generate a frequency control voltage and a switch circuit control signal based on the frequency difference between the clock signal and the input data signal, the frequency control voltage comprising a frequency down indication and a frequency up indication;
• and
• a voltage-to-current converter circuit coupled to the sampling circuit and configured to convert the frequency control voltage to a frequency control current in response to the switch circuit control signal, the voltage-to-current converter circuit comprising an output switch circuit controlled by the switch control signal and configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication;
• and
• a filter coupled to the phase detector and the reference-less frequency detector and configured to output a control signal to the voltage controlled oscillator, wherein the control signal provides an indication of a phase difference and a frequency difference between the input data signal and the clock signal.

A method for generating a frequency control signal from a reference-less frequency detector, the method comprising:

• generating an up/down control voltage, wherein the up/down control voltage is indicative of a frequency difference between an input data rate and a clock signal frequency, and comprises an up frequency indication voltage or a down frequency indication voltage;
• generating a control signal based on the data rate and the clock frequency;
• generating the frequency control current based on the up/down control voltage and the on/off control signal, wherein the on/off control signal controls an output switch circuit of a voltage-to-current converter circuit such that a latency of the up frequency indication voltage is equal to a latency of the down frequency indication voltage through the output switch circuit;
• and
• in response to detecting the input data rate is greater than the clock signal frequency, configuring the voltage-to-current converter circuit to operate in a frequency up mode.