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US 10,097,189 B2Granted
Semiconductor device
AssigneeRenesas Electronics Corporation
InventorsTakeshi Oshita, Takanori Hirota, Masato Suzuki
Life of this patent
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Abstract
A delay time is set only within the variable delay time of a clock driver and cannot be set longer than the variable delay time of the clock driver. A control circuit adjusts the delay amount of a variable delay circuit so as to synchronize a pulse phase after a first pulse outputted from a pulse generation circuit passes through the variable delay circuit N times and a second pulse outputted from the pulse generation circuit.
Claims9
A method for adjusting a delay amount of a first variable delay circuit, comprising the steps of:
- (a) generating a first pulse and a second pulse at a time subsequent to the first pulse;
- (b) selecting the first pulse as an input for the first variable delay circuit;
- (c) selecting an output from the first variable delay circuit as the input for the first variable delay circuit;
- and
- (d) adjusting the delay amount of the first variable delay circuit so as to synchronize an output pulse in the output of the first variable delay circuit with the second pulse after a repetition number of step (c) more than 2, wherein step (d) comprises the step of (d1) comparing a phase of the second pulse and a phase of the output pulse from the first variable delay circuit;
- and
- (e) selecting the second pulse as an input for the first variable delay circuit based on the repetition number of step (c):
- wherein the second pulse is a pulse subsequent to the first pulse.
5 more elements
A method for measuring a TDR, comprising the steps of:
- (a) generating a pulse and outputting the pulse to a transmit data path;
- (b) transmitting a first output pulse from the transmit data path to a receive data path;
- (c) selecting the pulse as an input to a variable delay circuit;
- (d) selecting an output of the variable delay circuit as the input to the variable delay circuit;
- and
- (e) adjusting a delay amount of a variable delay circuit so as to synchronize an output pulse in the output of the variable delay circuit with a second output pulse outputted from the receive data path after a repetition number of step (d) more than 2, wherein step (e) comprises the step of comparing a phase of the second output pulse and a phase of the output pulse from the first variable delay circuit;
- wherein the second output pulse is a pulse subsequent to the first output pulse.
4 more elements
Dependencies are inferred from the claim text.