Integrated circuit layout wiring for multi-core chips

A device, comprising:

• a channel-less integrated semiconductor die, including:
• a substrate;
• a plurality of lower metal levels formed on the substrate;
• a plurality of upper metal levels formed on the plurality of lower metal levels;
• a first logical unit having a plurality of transistors and passive circuity components formed within a first area of the substrate, the first logical unit including a first plurality of interconnection lines formed with the plurality of lower metal levels;
• a second logical unit having a plurality of transistors and passive circuity components formed within a second area of the substrate, the second logical unit including a second plurality of interconnection lines formed with the plurality of lower metal levels;
• a third logical unit having a plurality of transistors and passive circuity components formed within a third area of the substrate;
• and
• a first bus formed in a metal level of the plurality of upper metal levels that is furthest away from the substrate, the first bus coupled from the first logical unit to the second logical unit, the first bus extending across the third logical unit;
• and
• a buffer circuit electrically coupled to the first bus.

A device, comprising:

• a channel-less integrated semiconductor die, including:
• a substrate;
• a first plurality of conductive levels on the substrate;
• first, second, and third logical circuits in the substrate, each of the first, second, and third logical circuits including a plurality of interconnections formed from the first plurality of conductive levels;
• a second plurality of conductive levels that are spaced from the substrate by the first plurality of conductive levels, the second plurality of conductive levels including:
• a first bus electrically coupling the first logical circuit to the second logical circuit, the first bus extending across the third logical circuit;
• and
• a buffer circuit in the substrate, the buffer circuit being electrically coupled to the first bus, the first logical circuit being spaced from the second logical circuit by the buffer circuit.