US 10,097,169 B1Granted

Method and apparatus for reducing impact of transistor random mismatch in circuits

AssigneeMicron Technology, Inc.

InventorsDong Pan, John D. Porter

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Abstract

An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

Claims17

Dependent claims

An apparatus, comprising;

an analog circuit including a pair of analog circuit input nodes and a pair of analog circuit output nodes;
and
a mismatch reduction circuit including:
a first mismatch reduction circuit input node;
a first mismatch reduction circuit output node;
a phase controller configured to time one or more pairs of even and odd phases;
an input switch coupled to the phase controller and configured to electrically connect the first mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase of the one or more pairs of even and odd phases and to electrically connect the first mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase of the one or more pairs of even and odd phases;
an output switch coupled to the phase controller and configured to electrically connect a first node of the pair of analog circuit output nodes to the first mismatch reduction circuit output node during each even phase of the one or more pairs of even and odd phases and to electrically connect a second node of the pair of analog circuit output nodes to the first mismatch reduction circuit output node during each odd phase of the one or more pairs of even and odd phases;
and
an output circuit configured to record a signal at the first mismatch reduction circuit output node for each phase of the one or more pairs of even and odd phases and to produce an averaged signal being an average of the signals recorded for the one or more pairs of even and odd phases.

7 more elements

An apparatus, comprising:

an operational amplifier including:
a pair of operational amplifier input nodes including a non-inverting operational amplifier input node and an inverting operational amplifier input node;
and
a pair of complementary operational amplifier output nodes including a true operational amplifier output node and a complementary operational amplifier output node;
and
a mismatch reduction circuit coupled to the operational amplifier circuit and including:
first and second mismatch reduction circuit input nodes;
first and second mismatch reduction circuit output nodes;
a phase controller configured to time a first phase and a second phase;
an input switch coupled to the phase controller and configured to electrically connect the first mismatch reduction circuit input node to the non-inverting operational amplifier input node and the second mismatch reduction circuit input node to the inverting operational amplifier input node during the first phase and to electrically connect the first mismatch reduction circuit input node to the inverting operational amplifier input node and the second mismatch reduction circuit input node to the non-inverting operational amplifier input node during the second phase;
an output switch coupled to the phase controller and configured to electrically connect the true operational amplifier output node to the first mismatch reduction circuit output node and the complementary operational amplifier output node to the second mismatch reduction circuit output node during the first phase and to electrically connect the complementary operational amplifier output node to the first mismatch reduction circuit output node and the true operational amplifier output node to the second mismatch reduction circuit output node during the second phase;
and
an output circuit configured to record an output signal between the first and second mismatch reduction circuit output nodes during the first and second phases, and produce an averaged output signal being an average of the output signal recorded during the first phase and the output signal recorded during the second phase.

10 more elements

A method for reducing impact of transistor random mismatch in an electronic circuit, comprising:

processing an input signal to produce an output signal using an electronic circuit, the electronic circuit including an operational amplifier circuit having a pair of differential input nodes and a pair of complementary output nodes;
timing one or more pairs of even and odd phases;
transmitting the input signal to a first node of the pair of differential input nodes during each even phase of the one or more pairs of even and odd phases;
receiving the output signal from a first node of the pair complementary output nodes during each even phase;
transmitting the input signal to a second node of the pair of differential input nodes during each odd phase of the one or more pairs of even and odd phases;
receiving the output signal from a second node of the pair of complementary output nodes during each odd phase;
transmitting the input signal to the pair of differential input nodes during each even phase, the transmitted signal being a differential signal between the first and second nodes of the pair of differential input nodes;
receiving the output signal from the pair of complementary output nodes during each even phase, the received signal being a differential signal between the first and second nodes of the pair of complementary output nodes;
inverting the input signal and transmitting the inverted input signal to the pair of differential input nodes during each odd phase;
and
receiving the output signal from the pair of complementary output nodes and inverting the received output signal during each odd phase.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/482,020Filed 7 Apr 2017
Published: US 2018/0294806 A111 Oct 2018
Granted: 9 Oct 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification22 codes

H03F 3/393
With semiconductor devices only: with field-effect devices
H03K 5/007
Changing the DC level: base line stabilisation
H03F 3/45475
Characterised by the way of implementation of the active amplifying circuit in the differential amplifier: using IC blocks as the active…
H03F 3/45977
By using a feedback circuit: using switching means, e.g. sample and hold