Back to results
US 10,097,168 B2Granted
Current-mode clock distribution
AssigneeThe Regents of the University of California
InventorsMatthew Guthaus, Riadul Islam
Life of this patent
Estimating the term…
Abstract
Current-mode signaling for a one-to-many clock signal distribution providing significantly less dynamic power use and improved noise immunity compared to traditional VM signaling schemes.
Claims18
A current mode flip-flop, comprising:
- a first current mirror for receiving a voltage reference and for producing a first reference current in response to said voltage reference;
- a second current mirror for producing a second reference current;
- a current input for modifying said second reference current;
- a current comparator for producing a difference current between said first reference current and said modified second reference current;
- an inverting amplifier for converting said difference current into a logic level voltage;
- a pulse shaper receiving said logic level voltage and for applying a delayed version to said current comparator to thereby form a clock signal having a pulse duration;
- a register stage for receiving a data signal and said clock signal;
- and
- a storage cell for storing data when said clock signal occurs.
6 more elements
A very large scale integrated circuit, comprising:
- a voltage mode clock to current mode clock converter receiving a voltage mode clock and outputting a current mode clock;
- an H-Tree clock distribution network having at least a first current mode flip-flop and a second current mode flip-flop;
- and
- an interconnect connecting said current mode clock to said H-Tree clock distribution network;
- wherein said H-Tree clock distribution network evenly distributes said current mode clock to said first current mode flip-flop and to said second current mode flip-flop.
2 more elements
Dependencies are inferred from the claim text.